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X25080VI-2.7 PDF даташит

Спецификация X25080VI-2.7 изготовлена ​​​​«Xicor» и имеет функцию, называемую «SPI Serial E2PROM With Block LockTM Protection».

Детали детали

Номер произв X25080VI-2.7
Описание SPI Serial E2PROM With Block LockTM Protection
Производители Xicor
логотип Xicor логотип 

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X25080VI-2.7 Даташит, Описание, Даташиты
APPLICATION NOTE
AVA I L A B L E
X25080
AN61
8K
X25080
1K x 8 Bit
SPI Serial E2PROM With Block LockTM Protection
FEATURES
• 2MHz Clock Rate
• SPI Modes (0,0 & 1,1)
• 1K X 8 Bits
— 32 Byte Page Mode
• Low Power CMOS
— <1µA Standby Current
— <5mA Active Current
• 2.7V To 5.5V Power Supply
• Block Lock Protection
— Protect 1/4, 1/2 or all of E2PROM Array
• Built-in Inadvertent Write Protection
— Power-Up/Power-Down protection circuitry
— Write Enable Latch
— Write Protect Pin
• Self-Timed Write Cycle
— 5ms Write Cycle Time (Typical)
• High Reliability
— Endurance: 100,000 cycles
— Data Retention: 100 Years
— ESD protection: 2000V on all pins
• 8-Lead PDlP Package
• 8-Lead SOIC Package
• 14-Lead TSSOP Package
DESCRIPTION
The X25080 is a CMOS 8192-bit serial E2PROM,
internally organized as 1K x 8. The X25080 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is con-
trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25080 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25080 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25080 disabling all write attempts to the status
register, thus providing a mechanism for limiting end
user capability of altering 0, 1/4, 1/2 or all of the memory.
The X25080 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
X DECODE
LOGIC
8
8
16
1K BYTE
ARRAY
8 X 256
8 X 256
16 X 256
WRITE
CONTROL
AND
WP TIMING
LOGIC
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3090-1.7 6/11/96 T3/C1/D0 NS
1
32 8
Y DECODE
DATA REGISTER
3090 ILL F01
Characteristics subject to change without notice









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X25080VI-2.7 Даташит, Описание, Даташиты
X25080
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of the
serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25080 is deselected and the SO
output pin is at high impedance and unless an internal
write operation is underway, the X25080 will be in the
standby power mode. CS LOW enables the X25080,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25080 status register are
disabled, but the part otherwise functions normally.
When WP is held HIGH, all functions, including nonvola-
tile writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25080 status
register. If the internal write cycle has already been
initiated, WP going LOW will have no effect on a write.
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install the
X25080 in a system with WP pin grounded and still be
able to write to the status register. The WP pin functions
will be enabled when the WPEN bit is set “1”.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence
is underway, HOLD may be used to pause the serial
communication with the controller without resetting the
serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.
PIN CONFIGURATION
CS
SO
WP
VSS
DIP/SOIC
18
27
X25080
36
45
VCC
HOLD
SCK
SI
CS
SO
NC
NC
NC
WP
VSS
TSSOP
1 14
2 13
3 12
4 X25080 11
5 10
69
78
VCC
HOLD
NC
NC
NC
SCK
SI
3090 ILL F02.2
PIN NAMES
SYMBOL
CS
SO
SI
SCK
WP
VSS
VCC
HOLD
NC
DESCRIPTION
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
No Connect
3090 PGM T01
2









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X25080VI-2.7 Даташит, Описание, Даташиты
X25080
PRINCIPLES OF OPERATION
The X25080 is a 1K x 8 E2PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The X25080 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK. CS must be LOW and the HOLD and WP
inputs must be HIGH during the entire operation. The
WP input is “Don’t Care” if WPEN is set “0”.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are trans-
ferred MSB first.
Data input is sampled on the first rising edge of SCK after
CS goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations. If the clock line is
shared with other peripheral devices on the SPI bus, the
user can assert the HOLD input to place the X25080 into
a “PAUSE” condition. After releasing HOLD, the X25080
will resume operation from the point when HOLD was
first asserted.
Write Enable Latch
The X25080 contains a “write enable” latch. This latch
must be SET before a write operation will be completed
internally. The WREN instruction will set the latch and
the WRDI instruction will reset the latch. This latch is
automatically reset upon a power-up condition and after
the completion of a byte, page, or status register write
cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
7 654 3
2 10
WPEN X X X BP1 BP0 WEL WIP
3090 PGM T02
WPEN, BP0 and BP1 are set by the WRSR instruction.
WEL and WIP are read-only and automatically set by
other operations.
The Write-In-Process (WIP) bit indicates whether the
X25080 is busy with a write operation. When set to a “1”,
a write is in progress, when set to a “0”, no write is in
progress. During a write, all other bits are set to “1”.
The Write Enable Latch (WEL) bit indicates the status of
the “write enable” latch. When set to a “1”, the latch is set,
when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of protec-
tion. The X25080 is divided into four 2048-bit segments.
One, two, or all four of the segments may be protected.
That is, the user may read the segments but will be
unable to alter (write) data within the selected segments.
The partitioning is controlled as illustrated below.
Status Register Bits
BP1 BP0
00
01
10
11
Array Addresses
Protected
None
$0300–$03FF
$0200–$03FF
$0000–$03FF
3090 PGM T03
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
0000 0110
Set the Write Enable Latch (Enable Write Operations)
WRDI
0000 0100
Reset the Write Enable Latch (Disable Write Operations)
RDSR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register
READ
0000 0011
Read Data from Memory Array beginning at selected
address
WRITE
0000 0010
Write Data to Memory Array beginning at Selected Address
(1 to 32 Bytes)
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3090 PGM T04
3










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Номер в каталогеОписаниеПроизводители
X25080VI-2.7SPI Serial E2PROM With Block LockTM ProtectionXicor
Xicor

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