SC16C654IA68 Datasheet PDF - NXP Semiconductors
| Part Number | SC16C654IA68 | |
| Description | Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder | |
| Manufacturers | NXP Semiconductors | |
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SC16C654/654D
Quad UART with 64-byte FIFO and infrared (IrDA)
encoder/decoder
Rev. 04 — 19 June 2003
Product data
1. Description
The SC16C654/654D is a 4-channel Universal Asynchronous Receiver and
Transmitter (QUART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbits/s. It comes with an Intel or Motorola interface.
The SC16C654/654D is pin compatible with the ST16C654 and TL16C754 and it will
power-up to be functionally equivalent to the 16C454. Programming of control
registers enables the added features of the SC16C654/654D. Some of these added
features are the 64-byte receive and transmit FIFOs, automatic hardware or software
flow control and Infrared encoding/decoding. The selectable auto-flow control feature
significantly reduces software overload and increases system efficiency while in FIFO
mode by automatically controlling serial data flow using RTS output and CTS input
signals. The SC16C654/654D also provides DMA mode data transfers through FIFO
trigger levels and the TXRDY and RXRDY signals. On-board status registers provide
the user with error indications, operational status, and modem interface control.
System interrupts may be tailored to meet user requirements. An internal loop-back
capability allows on-board diagnostics.
The SC16C654/654D operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature
range, and is available in plastic PLCC68 and LQFP64 packages.
2. Features
s 5 V, 3.3 V and 2.5 V operation
s Industrial temperature range
s Pin compatibility with the industry-standard ST16C454/554, ST68C454/554,
TL16C554
s Up to 5 Mbits/s data rate at 5 V and 3.3 V and 3 Mbits/s at 2.5 V
s 64-byte transmit FIFO
s 64-byte receive FIFO with error flags
s Automatic software/hardware flow control
s Programmable Xon/Xoff characters
s Software selectable Baud Rate Generator
s Four selectable Receive and Transmit FIFO interrupt trigger levels
s Standard modem interface or infrared IrDA encoder/decoder interface
s Sleep mode
s Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)
s Transmit, Receive, Line Status, and Data Set interrupts independently controlled
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Philips Semiconductors
SC16C654/654D
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
5. Pinning information
5.1 Pinning
5.1.1 PLCC68
DSRA 10
CTSA 11
DTRA 12
VCC 13
RTSA 14
INTA 15
CSA 16
TXA 17
IOW 18
TXB 19
CSB 20
INTB 21
RTSB 22
GND 23
DTRB 24
CTSB 25
DSRB 26
SC16C654IA68
16 MODE
Fig 3. PLCC68 pin configuration (16 mode).
60 DSRD
59 CTSD
58 DTRD
57 GND
56 RTSD
55 INTD
54 CSD
53 TXD
52 IOR
51 TXC
50 CSC
49 INTC
48 RTSC
47 VCC
46 DTRC
45 CTSC
44 DSRC
002aaa203
9397 750 11617
Product data
Rev. 04 — 19 June 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ SC16C654IA68.PDF Datasheet ] | |
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