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PDF 6818 Data sheet ( Hoja de datos )
| Número de pieza | 6818 | |
| Descripción | DABiC-IV/ 32-BIT SERIAL-INPUT/ LATCHED SOURCE DRIVER | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 6818 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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6818
A6818xA
LOAD
SUPPLY
1
VBB
SERIAL
DATA OUT
2
OUT 32 3
OUT 31 4
OUT 30 5
OUT 29 6
OUT 28 7
OUT27 8
OUT26 9
OUT25 10
OUT 24 11
OUT 23 12
OUT22 13
OUT21 14
OUT 20 15
OUT19 16
OUT 18 17
OUT17 18
BLANKING 19 BLNK
GROUND 20
VDD
40
LOGIC
SUPPLY
39
SERIAL
DATA IN
38 OUT 1
37 OUT 2
36 OUT 3
35 OUT 4
34 OUT5
33 OUT 6
32 OUT7
31 OUT8
30 OUT9
29 OUT 10
28 OUT 11
27 OUT 12
26 OUT 13
25 OUT 14
24 OUT 15
23 OUT 16
ST 22 STROBE
CLK 21 CLOCK
Dwg. PP-029-4
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD ................... 7.0 V
Driver Supply Voltage, VBB ................... 60 V
Continuous Output Current Range,
IOUT ......................... -40 mA to +15 mA
Input Voltage Range,
VIN ....................... -0.3 V to VDD + 0.3 V
Package Power Dissipation,
PD ........................................ See Graph
Operating Temperature Range, TA
(Suffix ‘E–’) .................. -40°C to +85°C
(Suffix ‘S–’) .................. -20°C to +85°C
Storage Temperature Range,
TS ............................... -55°C to +125°C
Caution: These CMOS devices have input
static protection (Class 2) but are still
susceptible to damage if exposed to
extremely high static electrical charges.
DABiC-IV, 32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
The A6818– devices combine a 32-bit CMOS shift register,
accompanying data latches and control circuitry with bipolar sourcing
outputs and pnp active pull downs. Designed primarily to drive
vacuum-fluorescent displays, the 60 V and -40 mA output ratings also
allow these devices to be used in many other peripheral power driver
applications. The A6818– features an increased data input rate (com-
pared with the older UCN/UCQ5818–F) and a controlled output slew
rate.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply,
typical serial-data input rates are up to 33 MHz.
A CMOS serial data output permits cascade connections in applica-
tions requiring additional drive lines. Similar devices are available as
the A6809– and A6810– (10 bits), A6811– (12 bits), and A6812– (20
bits).
The A6818– output source drivers are npn Darlingtons, capable of
sourcing up to 40 mA. The controlled output slew rate reduces electro-
magnetic noise, which is an important consideration in systems that
include telecommunications and/or microprocessors and to meet
government emissions regulations. For inter-digit blanking, all output
drivers can be disabled and all sink drivers turned on with a BLANK-
ING input high. The pnp active pull-downs will sink at least 2.5 mA.
Two temperature ranges are available for optimum performance in
commercial (suffix S-) or industrial (suffix E-) applications. Package
styles are provided for through-hole DIP (suffix -A) or minimum-area
surface-mount PLCC (suffix -EP). Copper lead frames, low logic-
power dissipation, and low output-saturation voltages allow these
devices to drive most multiplexed vacuum-fluorescent displays over
the maximum operating temperature range.
FEATURES
I Controlled Output Slew Rate I Low Output-Saturation Voltages
I High-Speed Data Storage I Low-Power CMOS Logic
I 60 V Minimum
and Latches
Output Breakdown
I Improved Replacements
I High Data Input Rate
for SN75518N, SN75518NF,
I PNP Active Pull-Downs
UCN5818–, and UCQ5818–
Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A or -EP). Always
order by complete part number, e.g., A6818SEP .
1 page  
6818
32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
CLOCK
50%
SERIAL
DATA IN
SERIAL
DATA OUT
AB
DATA
50%
t p(CH-SQX)
50%
DE
DATA
STROBE
50%
BLANKING
OUT N
LOW = ALL OUTPUTS ENABLED
t p(STH-QH)
t p(STH-QL)
90%
DATA
10%
Dwg. WP-029
BLANKING
OUT N
HIGH = ALL OUTPUTS BLANKED (DISABLED)
50%
t en(BQ)
t dis(BQ)
tr
DATA
10%
tf
90%
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ......................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ............................................... 25 ns
C. Clock Pulse Width, tw(CH) ............................................... 50 ns
D. Time Between Clock Activation and Strobe, tsu(C) ....... 100 ns
E. Strobe Pulse Width, tw(STH) ............................................. 50 ns
NOTE – Timing is representative of a 10 MHz clock. Signifi-
cantly higher speeds are attainable.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Dwg. WP-030
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
www.allegromicro.com
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 6818.PDF ] | |
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