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54165DMQB PDF даташит

Спецификация 54165DMQB изготовлена ​​​​«National Semiconductor» и имеет функцию, называемую «8-Bit Parallel-to-Serial Converter».

Детали детали

Номер произв 54165DMQB
Описание 8-Bit Parallel-to-Serial Converter
Производители National Semiconductor
логотип National Semiconductor логотип 

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54165DMQB Даташит, Описание, Даташиты
August 1989
54165 DM74165
8-Bit Parallel-to-Serial Converter
General Description
The ’165 is an 8-bit parallel load or serial-in register with
complementary outputs available from the last stage Paral-
lel inputting occurs asynchronously when the Parallel Load
(PL) input is LOW With PL HIGH serial shifting occurs on
the rising edge of the clock new data enters via the Serial
Data (DS) input The 2-input OR clock can be used to com-
bine two independent clock sources or one input can act as
an active LOW clock enable
Connection Diagram
Logic Symbol
Dual-In-Line-Package
VCC e Pin 16
GND e Pin 8
TL F 9782 – 1
Order Number 54165DMQB 54165FMQB or DM74165N
See NS Package Number J16A N16E or W16A
Pin Names
CP1 CP2
DS
PL
P0 – P7
Q7
Q7
Description
Clock Pulse Inputs (Active Rising Edge)
Serial Data Input
Asynchronous Parallel Load Input
(Active LOW)
Parallel Data Inputs
Serial Output from Last Stage
Complementary Output
TL F 9782 – 2
C1995 National Semiconductor Corporation TL F 9782
RRD-B30M115 Printed in U S A









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54165DMQB Даташит, Описание, Даташиты
Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage
7V
Input Voltage
5 5V
Operating Free Air Temperature Range
54 b55 C to a125 C
DM74
0 C to a70 C
Storage Temperature Range
b65 C to a150 C
Note The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
TA
ts(H)
ts(L)
th(H)
th(L)
ts(H)
ts(L)
th(H)
th(L)
ts(H)
tw(H)
tw(L)
trec
Parameter
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating Temperature
Setup Time HIGH or LOW
Pn to PL
Hold Time HIGH or LOW
Pn to PL
Setup Time HIGH or LOW
DS to CPn
Hold Time HIGH or LOW
DS to CPn
Setup Time HIGH
CP1 to CP2 or CP2 to CP1
CPn Pulse Width HIGH
PL Pulse Width LOW
Recovery Time PL to CPn
Min
45
2
b55
10
10
10
10
20
20
0
0
30
25
15
45
54165
Nom
5
Max
55
08
b0 8
16
125
DM74165
Min Nom Max
4 75 5
5 25
2
08
b0 8
16
0 70
10
10
0
0
20
20
0
0
30
25
15
45
Units
V
V
V
mA
mA
C
ns
ns
ns
ns
ns
ns
ns
ns
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
VI
VOH
VOL
II
IIH
IIL
IOS
ICC
Parameter
Input Clamp Voltage
High Level Output Voltage
Low Level Output Voltage
Input Current Max
Input Voltage
High Level Input Current
Low Level Input Current
Short Circuit
Output Current
Supply Current
Conditions
VCC e Min II e b12 mA
VCC e Min IOH e Max VIL e Max
VCC e Min VIH e Min
VCC e Max VI e 5 5V
VCC e Max VI e 2 4V
VCC e Max VI e 0 4V
VCC e Max
(Note 2)
VCC e Max PL e
Pn e K CP1 CP2 e 4 5V
PL
Inputs
PL
Inputs
54
DM74
Min
24
b20
b18
Typ
(Note 1)
34
02
Max
b1 5
04
1
80
40
b3 2
b1 6
b55
b55
63
Units
V
V
V
mA
mA
mA
mA
mA
2









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54165DMQB Даташит, Описание, Даташиты
Switching Characteristics
VCC e a5 0V TA e a25 C (See Section 1 for waveforms and load configurations)
Symbol
Parameter
CL e 15 pF
RL e 400X
Min Max
fmax
Maximum Clock Frequency
tPLH
tPHL
Propagation Delay
PL to Q7 or Q7
tPLH
tPHL
Propagation Delay
CP1 to Q7 or Q7
tPLH
tPHL
Propagation Delay
P7 to Q7
tPLH
tPHL
Propagation Delay
P7 to Q7
Note 1 All typicals are at VCC e 5V TA e 25 C
Note 2 Not more than one output should be shorted at a time
20
31
40
24
31
17
36
27
27
Units
MHz
ns
ns
ns
ns
Functional Description
The ’165 contains eight clocked master slave RS flip-flops
connected as a shift register with auxiliary gating to provide
overriding asynchronous parallel entry Parallel data enters
when the PL signal is LOW The parallel data can change
while PL is LOW provided that the recommended setup and
hold times are observed
For clocked operation PL must be HIGH The two clock
inputs perform identically one can be used as a clock inhibit
Truth Table
CP
PL
Contents
1 2 Q0 Q1 Q2 Q3 Q4
LX
X P0 P1 P2 P3 P4
H L L DS Q0 Q1 Q2 Q3
H H L Q0 Q1 Q2 Q3 Q4
H L L DS Q0 Q1 Q2 Q3
H L H Q0 Q1 Q2 Q3 Q4
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e Positive Rising Edge
Logic Diagram
by applying a HIGH signal To avoid double clocking how-
ever the inhibit signal should only go HIGH while the clock
is HIGH Otherwise the rising inhibit signal will cause the
same response as a rising clock edge The flip-flops are
edge-triggered for serial operations The serial input data
can change at any time provided only that the recommend-
ed setup and hold times are observed with respect to the
rising edge of the clock
Q5 Q6 Q7
Response
P5 P6 P7 Parallel Entry
Q4 Q5 Q6 Right Shift
Q5 Q6 Q7 No Change
Q4 Q5 Q6 Right Shift
Q5 Q6 Q7 No Change
TL F 9782 – 3
3










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Номер в каталогеОписаниеПроизводители
54165DMQB8-Bit Parallel-to-Serial ConverterNational Semiconductor
National Semiconductor

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