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M-8870-01SM PDF даташит

Спецификация M-8870-01SM изготовлена ​​​​«Clare Inc.» и имеет функцию, называемую «DTMF Receiver».

Детали детали

Номер произв M-8870-01SM
Описание DTMF Receiver
Производители Clare Inc.
логотип Clare  Inc. логотип 

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M-8870-01SM Даташит, Описание, Даташиты
Features
Low Power Consumption
Adjustable Acquisition and Release Times
Central Office Quality and Performance
Power-down and Inhibit Modes (-02 only)
Inexpensive 3.58 MHz Time Base
Single 5 Volt Power Supply
Dial Tone Suppression
Applications
Telephone switch equipment
Remote data entry
Paging systems
Personal computers
Credit card systems
Pin Configuration
Block Diagram
M-8870
DTMF Receiver
Description
The M-8870 is a full DTMF Receiver that integrates
both bandsplit filter and decoder functions into a single
18-pin DIP or SOIC package. Manufactured using
CMOS process technology, the M-8870 offers low
power consumption (35 mW max) and precise data
handling. Its filter section uses switched capacitor
technology for both the high and low group filters and
for dial tone rejection. Its decoder uses digital counting
techniques to detect and decode all 16 DTMF tone
pairs into a 4-bit code. External component count is
minimized by provision of an on-chip differential input
amplifier, clock generator, and latched tri-state inter-
face bus. Minimal external components required
include a low-cost 3.579545 MHz color burst crystal, a
timing resistor, and a timing capacitor.
The M-8870-02 provides a “power-down” option
which, when enabled, drops consumption to less
than 0.5 mW. The M-8870-02 can also inhibit the
decoding of fourth column digits (see Tone Decoding
table on page 5).
Ordering Information
Part #
M-8870-01
Description
18-pin plastic DIP
M-8870-01SM 18-pin plastic SOIC
M-8870-01SMTR 18-pin plastic SOIC, tape and reel
M-8870-02
18-pin plastic DIP, power-down,
option
M-8870-02SM
18-pin plastic SOIC, power-down,
option
M-8870-02T
18-pin plastic SOIC, power-down
option, tape and reel
DS-M8870-R3
www.clare.com
1









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M-8870-01SM Даташит, Описание, Даташиты
M-8870
Absolute Maximum Ratings
Parameter
Symbol
Value
Power supply voltage (VDD - VSS) VDD
6.0 V max
Voltage on any pin
VDC VSS -0.3, VDD +0.3
Current on any pin
IDD 10 mA max
Operating temperature
TA -40°C to + 85°C
Storage temperature
TS -65°C to + 150°C
Note:
Exceeding these ratings may cause permanent damage. Functional operation under
these conditions is not implied.
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to the absolute maximum ratings for an extend-
ed period may degrade the device and effect its reliability.
DC Characteristics
Parameter
Symbol
Min
Typ Max
Operating supply voltage
Operating supply current
Standby supply current (see Note 3)
Power consumption
Low level input voltage
High level input voltage
Input leakage current
Pullup (source) current on OE
Input impedance, signal inputs 1, 2
Steering threshold voltage
Low level output voltage
High level output voltage
Output low (sink) current
Output high (source) current
Output voltage VREF
Output resistance VREF
VDD
IDD
IDDQ
PO
VIL
VIH
IIH/IIL
ISO
RIN
VTSt
VOL
VOH
IOL
IOH
VREF
ROR
4.75
-
-
-
-
3.5
-
-
8
2.2
-
VDD - 0.03
1.0
0.4
2.4
-
-
3.0
-
15
-
-
0.1
6.5
10
-
-
-
2.5
0.8
-
10
5.25
7.0
100
35
1.5
-
-
15.0
-
2.5
0.03
-
-
-
2.7
-
*Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Units
V
mA
µA
mW
V
V
µA
µA
m
V
V
V
mA
mA
V
k
Test Conditions
-
-
PD=VDD
f = 3.579 MHz, VDD = 5.0 V
-
-
VIN = VSS or VDD (see Note 2)
OE = 0 V
@ 1 kHz
-
No load
No load
VOUT = 0.4 V
VOUT = VDD - 0.4 V
No load
-
Operating Characteristics - Gain Setting Amplifier
Parameter
Symbol
Min
Typ Max
Input leakage current
Input resistance
Input offset voltage
Power supply rejection
IN
-
± 100
-
RIN 4
--
VOS - ± 25 -
PSRR
50
--
Common mode rejection
CMRR
55
--
DC open loop voltage gain
Open loop unity gain bandwidth
Output voltage swing
Tolerable capacitive load (GS)
Tolerable resistive load (GS)
Common mode range
AVOL
60
--
fC 1.2 1.5 -
VO 3.5 - -
CL - - 100
RL - - 50
VCM 2.5
--
*Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Notes:
1. All voltages referenced to VSS unless otherwise noted. For typical values, VDD = 5.0V, VSS = 0V, TA = 25°C.
Units
nA
M
mV
dB
dB
dB
MHz
VP-P
pF
k
VP-P
2 www.clare.com
Test Conditions
VSS < VIN < VDD
-
-
1 KHz
-3.0V < VIN < 3.0V
-
-
RL 100 Kto VSS
-
-
No load
Rev. 3









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M-8870-01SM Даташит, Описание, Даташиты
M-8870
Functional Description
M-8870 operating functions (see block diagram on
page 1) include a bandsplit filter that separates the
high and low tones of the received pair, and a digital
decoder that verifies both the frequency and duration
of the received tones before passing the resulting 4-bit
code to the output bus.
Filter
The low and high group tones are separated by apply-
ing the dual-tone signal to the inputs of two 6th order
switched capacitor bandpass filters with bandwidths
that correspond to the bands enclosing the low and
high group tones. The filter also incorporates notches
at 350 and 440 Hz, providing excellent dial tone rejec-
tion. Each filter output is followed by a single-order
switched capacitor section that smooths the signals
prior to limiting. Signal limiting is performed by high-
gain comparators provided with hysteresis to prevent
detection of unwanted low-level signals and noise.
The comparator outputs provide full-rail logic swings
at the frequencies of the incoming tones.
Decoder
The M-8870 decoder uses a digital counting tech-
nique to determine the frequencies of the limited tones
and to verify that they correspond to standard DTMF
frequencies. A complex averaging algorithm is used to
protect against tone simulation by extraneous signals
(such as voice) while tolerating small frequency varia-
tions. The algorithm ensures an optimum combination
of immunity to talkoff and tolerance to interfering sig-
nals (third tones) and noise. When the detector rec-
ognizes the simultaneous presence of two valid tones
(known as signal condition), it raises the Early
Steering flag (ESt). Any subsequent loss of signal
condition will cause ESt to fall.
Basic Steering Circuit
Steering Circuit
Before a decoded tone pair is registered, the receiver
checks for a valid signal duration (referred to as char-
acter-recognition-condition). This check is performed
by an external RC time constant driven by ESt. A logic
high on ESt causes VC (see block diagram on page 1)
to rise as the capacitor discharges. Provided that sig-
nal condition is maintained (ESt remains high) for the
validation period (tGTF), VC reaches the threshold (VTSt)
of the steering logic to register the tone pair, thus latch-
ing its corresponding 4-bit code (see DC
Characteristics on page 2) into the output latch. At this
point, the GT output is activated and drives VC to VDD.
GT continues to drive high as long as ESt remains
high. Finally, after a short delay to allow the output
latch to settle, the delayed steering output flag (StD)
goes high, signaling that a received tone pair has been
registered. The contents of the output latch are made
available on the 4-bit output bus by raising the three-
state control input (OE) to a logic high. The steering
circuit works in reverse to validate the interdigit pause
between signals. Thus, as well as rejecting signals too
short to be considered valid, the receiver will tolerate
signal interruptions (dropouts) too short to be consid-
ered a valid pause. This capability, together with the
ability to select the steering time constants externally,
allows the designer to tailor performance to meet a
wide variety of system requirements.
Single-Ended Input Configuration
Rev. 3 www.clare.com
3










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Номер в каталогеОписаниеПроизводители
M-8870-01SMDTMF ReceiverClare  Inc.
Clare Inc.
M-8870-01SMTRDTMF ReceiverClare  Inc.
Clare Inc.

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