3968 Datasheet PDF - Allegro MicroSystems
| Part Number | 3968 | |
| Description | DUAL FULL-BRIDGE PWM MOTOR DRIVER WITH BRAKE | |
| Manufacturers | Allegro MicroSystems | |
| Logo |  |
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3968
ADVANCE INFORMATION
(subject to change without notice)
September 3, 1999
A3968SLB
OUT1A 1
INPUT1A 2
INPUT1B 3
GROUND 4
VBB
LOGIC LOGIC
16 OUT2A
15 INPUT2A
14 INPUT2B
13 GROUND
SENSE 1 5
OUT1B 6
LOAD
SUPPLY 7
VBB
REFERENCE 8 VREF
12 SENSE 2
11 OUT 2B
V CC
10
LOGIC
SUPPLY
RC 9 RC
Dwg. PP-066
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, VBB ................... 30 V
Output Current, IOUT (peak) .......... ±750 mA
(continuous) .............................. ±650 mA
Logic Supply Voltage, VCC ................. 7.0 V
Input Voltage, Vin ..... -0.3 V to VCC + 0.3 V
Sense Voltage, VS ................................ 1.0 V
Package Power Dissipation (TA = 25°C), PD
A3968SA ................................... 2.08 W*
A3968SLB ................................. 1.87 W*
Operating Temperature Range,
TA ................................... -20°C to +85°C
Junction Temperature,
TJ ................................................. +150°C
Storage Temperature Range,
TS ................................. -55°C to +150°C
Output current rating may be limited by duty
cycle, ambient temperature, and heat sinking.
Under any set of conditions, do not exceed the
specified current rating or a junction temperature
of 150°C.
* Per SEMI G42-88 Specification, Thermal Test
Board Standardization for Measuring Junction-
to-Ambient Thermal Resistance of Semiconductor
Packages.
DUAL FULL-BRIDGE PWM
MOTOR DRIVER WITH BRAKE
The A3968SA and A3968SLB are designed to bidirectionally control two
dc motors. Each device includes two H-bridges capable of continuous output
currents of ±650 mA and operating voltages to 30 V. Motor winding current
can be controlled by the internal fixed-frequency, pulse-width modulated
(PWM), current-control circuitry. The peak load current limit is set by the
user’s selection of a reference voltage and current-sensing resistors. Except
for package style and pinout, the two devices are identical.
The fixed-frequency pulse duration is set by a user-selected external
RC timing network. The capacitor in the RC timing network also determines
a user-selectable blanking window that prevents false triggering of the PWM
current-control circuitry during switching transitions.
To reduce on-chip power dissipation, the H-bridge power outputs have
been optimized for low saturation voltages. The sink drivers feature Allegro’s
patented Satlington™ output structure. The Satlington outputs combine the
low voltage drop of a saturated transistor and the high peak current capability
of a Darlington.
For each bridge, the INPUTA and INPUTB terminals determine the load
current polarity by enabling the appropriate source and sink driver pair.
When a logic low is applied to both INPUTs of a bridge, the braking function
is enabled. In brake mode, both source drivers are turned OFF and both sink
drivers are turned ON, thereby dynamically braking the motor. When a logic
high is applied to both INPUTs of a bridge, all output drivers are disabled.
Special power-up sequencing is not required. Internal circuit protection
includes thermal shutdown with hysteresis, ground-clamp and flyback diodes,
and crossover-current protection.
The A3968SA is supplied in a 16-pin dual in-line plastic package. The
A3968SLB is supplied in a 16-lead plastic SOIC with copper heat sink tabs.
The power tab is at ground potential and needs no electrical isolation.
FEATURES
s ±650 mA Continuous Output Current
s 30 V Output Voltage Rating
s Internal Fixed-Frequency PWM Current Control
s Satlington™ Sink Drivers
s Brake Mode
s User-Selectable Blanking Window
s Internal Ground-Clamp & Flyback Diodes
s Internal Thermal-Shutdown Circuitry
s Crossover-Current Protection and UVLO Protection
Always order by complete part number:
Part Number Package
A3968SA
16-pin DIP
A3968SLB
16-lead batwing SOIC
RθJA
60°C/W
67°C/W
RθJC
38°C/W
—
RθJT
—
6°C/W
|
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3968
DUAL FULL-BRIDGE
PWM MOTOR DRIVER
WITH BRAKE
FUNCTIONAL DESCRIPTION
Internal PWM Current Control. The A3968SA and
A3968SLB dual H-bridges are designed to bidirectionally
control two dc motors. An internal fixed-frequency PWM
current-control circuit controls the load current in each
motor. The current-control circuitry works as follows:
when the outputs of the H-bridge are turned on, current
increases in the motor winding. The load current is sensed
by the current-control comparator via an external sense
resistor (RS). Load current continues to increase until it
reaches the predetermined value, set by the selection of
external current-sensing resistors and reference input
voltage (VREF) according to the equation:
ITRIP = IOUT + ISO = VREF/(4 RS)
where ISO is the sense-current error (typically 18 mA) due
to the base-drive current of the sink driver transistor.
At the trip point, the comparator resets the source-
enable latch, turning off the source driver of that H-bridge.
The source turn off of one H-bridge is independent of the
other H-bridge. Load inductance causes the current to
recirculate through the sink driver and ground-clamp
diode. The current decreases until the internal clock
oscillator sets the source-enable latches of both H-bridges,
turning on the source drivers of both bridges. Load current
increases again, and the cycle is repeated.
The frequency of the internal clock oscillator is set by
INPUT A
the external timing components RTCT. The frequency can
be approximately calculated as:
fosc = 1/(RT CT + tblank)
where tblank is defined below.
The range of recommended values for RT and CT are
20 kΩ to 100 kΩ and 470 pF to 1000 pF respectively.
Nominal values of 56 kΩ and 680 pF result in a clock
frequency of 25.4 kHz.
Current-Sense Comparator Blanking. When the
source driver is turned on, a current spike occurs due to
the reverse-recovery currents of the clamp diodes and
switching transients related to distributed capacitance in
the load. To prevent this current spike from erroneously
resetting the source enable latch, the current-control
comparator output is blanked for a short period of time
when the source driver is turned on. The blanking time is
set by the timing component CT according to the equa-
tion:
tblank = 1900 CT (µs).
A nominal CT value of 680 pF will give a blanking
time of 1.3 µs.
The current-control comparator is also blanked when
the load current changes polarity (direction or phase
change). This internally generated blank time is approxi-
mately 1.8 µs.
INPUT B
+
I OUTB 0
–
BRIDGE
ON
"FORWARD"
ALL
OFF
"REVERSE"
V
BB
BRIDGE ON
SOURCE OFF
BRIDGE
ON
INTERNAL
OSCILLATOR
ITRIP
td
RTC T
SOURCE
OFF
tblank
Dwg. WM-003-3
ALL OFF
RS
Dwg. EP-006-16
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| Information | Total 12 Pages | |
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