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PDF CXK77P18E160GB-4BE Data sheet ( Hoja de datos )
| Número de pieza | CXK77P18E160GB-4BE | |
| Descripción | 16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18) | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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SONY® CXK77P36E160GB / CXK77P18E160GB 4/42/43/44
16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)
8Mb LW R-L w/ EC HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18)
Preliminary
Description
The CXK77P36E160GB (organized as 524,288 words by 36 bits) and the CXK77P18E160GB (organized as 1,048,576 words
by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input
registers, high speed RAM, output latches, and a one-deep write buffer onto a single monolithic IC. Register - Latch (R-L) read
operations and Late Write (LW) write operations are supported, providing a high-performance user interface.
Two distinct R-L modes of operation are supported, selectable via the M2 mode pin. When M2 is “high”, these devices function
as conventional 16Mb R-L SRAMs, and pin 2B functions as a conventional SA address input. When M2 is “low”, these devices
function as Error-Correcting (EC) 8Mb R-L SRAMs, and pin 2B is ignored.
When Error-Correcting 8Mb R-L mode is selected, the SRAM is divided into two banks internally - a “primary” bank and a
“secondary” bank. During write operations, input data is ultimately written to both banks internally (through one stage of write
pipelining). During read operations, data is read from both banks internally, and each byte of primary bank data is individually
parity-checked. If the parity of a particular byte of primary data is correct (that is, “odd”), it is driven valid externally. If the
parity of a particular byte of primary data is incorrect (that is, “even”), it is discarded, and the corresponding byte of secondary
bank data is driven valid externally. Primary / secondary bank data selection is performed on each data byte independently.
Data read from the secondary bank is NOT parity-checked.
Data read from the write buffer is NOT parity-checked.
All address and control input signals except ZZ (Sleep Mode) are registered on the rising edge of K (Input Clock).
During read operations, output data is driven valid from the falling edge of K, one half clock cycle after the address is registered.
During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.
The output drivers are series terminated, and the output impedance is programmable through an external impedance matching
resistor RQ. By connecting RQ between ZQ and VSS, the output impedance of all DQ pins can be precisely controlled.
Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single
3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
Features
• 4 Speed Bins
-4 (-4A) (-4B)
-42 (-42A) (-42B)
-43 (-43A) (-43B)
-44
Cycle Time / Access Time
4.0ns / 3.9ns (3.8ns) (3.7ns)
4.2ns / 4.2ns (4.1ns) (4.0ns)
4.3ns / 4.5ns (4.4ns) (4.3ns)
4.4ns / 4.7ns
• Single 3.3V power supply (VDD): 3.3V ± 5%
• Dedicated output supply voltage (VDDQ): 1.9V typical
• HSTL-compatible I/O interface with dedicated input reference voltage (VREF): 0.85V typical
• Register - Latch (R-L) read operations
• Late Write (LW) write operations
• Conventional 16Mb or Error-Correcting (EC) 8Mb mode of operation, selectable via dedicated mode pin (M2)
• Full read/write coherency
• Byte Write capability
• One cycle deselect
• Differential input clocks (K/K)
• Programmable impedance output drivers
• Sleep (power down) mode via dedicated mode pin (ZZ)
• JTAG boundary scan (subset of IEEE standard 1149.1)
• 119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
1 / 25
March 2, 2001
1 page  
SONY®
•Clock Truth Table
CXK77P36E160GB / CXK77P18E160GB
K
ZZ
SS
(tn)
SW SBWx
(tn) (tn)
Operation
XHXX
X Sleep (Power Down) Mode
L→H L H X
L→H L L H
L→H L L L
L→H L L L
L→H L L L
X Deselect
X Read
L Write All Bytes
X Write Bytes With SBWx = L
H Abort Write
Preliminary
DQ
(tn)
Hi - Z
Hi - Z
Q(tn)
Hi - Z
Hi - Z
Hi - Z
DQ
(tn+1)
Hi - Z
X
X
D(tn)
D(tn)
X
•Dynamic M2 Mode Pin State Changes
Although M2 is defined as a static input (that is, it must be tied “high” or “low” at power-up), in some instance (such as
during device testing) it may be desirable to change its state dynamically (that is, without first powering off the SRAM)
while preserving the contents of the memory array. If so, the following criteria must be met:
1. At least two (2) consecutive deselect operations must be initiated prior to changing the state of M2, to ensure that the
most recent read or write operation completes successfully.
2. At least thirty-two (32) consecutive deselect operations must be initiated after changing the state of M2 before any read
or write operations can be initiated, to allow the SRAM sufficient time to recognize the change in state.
•Sleep (Power Down) Mode
Sleep (power down) mode is provided through the asynchronous input signal ZZ. When ZZ is asserted (high), the output
drivers will go to a Hi-Z state, and the SRAM will begin to draw standby current. Contents of the memory array will be
preserved. An enable time (tZZE) must be met before the SRAM is guaranteed to be in sleep mode, and a recovery time
(tZZR) must be met before the SRAM can resume normal operation.
•Programmable Impedance Output Drivers
These devices have programmable impedance output drivers. The output impedance is controlled by an external resistor,
RQ, connected between the SRAM’s ZQ pin and VSS, and is equal to one-fifth the value of this resistor, nominally. See
the DC Electrical Characteristics section for further information.
The output impedance is updated whenever the output drivers are in a Hi-Z state. Consequently, impedance updates will
occur during write and deselect operations. At power up, 8192 clock cycles followed by an impedance update via one of
the three methods described above are required to ensure that the output impedance has reached the desired value. After
power up, periodic impedance updates via write or deselect operations are also required to ensure that the output imped-
ance remains within specified tolerances.
•Power-Up Sequence
For reliability purposes, Sony recommends that power supplies power up in the following sequence: VSS, VDD, VDDQ,
VREF, and Inputs. VDDQ should never exceed VDD. If this power supply sequence cannot be met, a large bypass diode
may be required between VDD and VDDQ. Please contact Sony Memory Application Department for further information.
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
5 / 25
March 2, 2001
5 Page 
SONY®
•AC Test Conditions
CXK77P36E160GB / CXK77P18E160GB
(VDD = 3.3V ± 5%, VDDQ = 1.9V ± 0.1V, TA = 0 to 85°C)
Item
Input Reference Voltage
Address / Control Input High Level
Address / Control Input Low Level
Data Input High Level
Data Input Low Level
Input Rise & Fall Time
Input Reference Level
Clock Input High Voltage
Clock Input Low Voltage
Clock Input Common Mode Voltage
Clock Input Rise & Fall Time
Clock Input Reference Level
Output Reference Level
Symbol
VREF
VCAIH
VCAIL
VDIH
VDIL
VKIH
VKIL
VCM
Conditions
0.85
1.45
0.35
1.25
0.55
2.0
0.85
1.45
0.75
1.10
2.0
K/K cross
0.95
Units
V
V
V
V
V
V/ns
V
V
V
V
V/ns
V
V
Output Load Conditions
Preliminary
Notes
VDIF = 0.7V
VDIF = 0.7V
Fig.1
RQ = 250Ω
Figure 1: AC Test Output Load
DQ 16.7 Ω
16.7 Ω
50 Ω
16.7 Ω
50 Ω
0.95 V
50 Ω
5 pF
0.95 V
50 Ω
5 pF
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
11 / 25
March 2, 2001
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet CXK77P18E160GB-4BE.PDF ] | |
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