|
|
PDF CXD1958Q Data sheet ( Hoja de datos )
| Número de pieza | CXD1958Q | |
| Descripción | MMDS TCM/QAM Demodulator + FEC + ADC | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CXD1958Q (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
CXD1958Q
MMDS TCM/QAM Demodulator + FEC + ADC Preliminary
Description
The CXD1958Q is an integrated TCM/QAM
demodulator for MMDS systems using the DAVIC
MMDS standard. This highly integrated device
incorporates an internal 8-bit ADC, image rejection
and root-raised cosine filters, all-digital symbol timing
recovery PLL, adaptive decision feedback equalizer
(DFE) with 10 feedforward and 30 feedback taps, 4-D
TCM decoder, and DAVIC/DVB compliant forward
error correction comprising (204,188) Reed Solomon
decoder, a programmable de-interleaver with I = 12
and I = 204, and a de-randomiser. All internal clocks
are generated from a single external 30MHz reference
crystal.
Device functionality also includes 3-wire bus interface
for configuring up to 2 tuner synthesizers, a sigma
delta tuner IF-AGC output, a user programmable RF-
AFC sigma delta output, spectrum inversion of the
received signal for tuner compatibility, and a highly
configurable MPEG2-TS interface. An I2C bus
interface provides on-board configuration and status
monitoring of various functions including access to
the equalizer tap values and constellation points.
JTAG provides boundary scan test compatibility.
Features
• DAVIC MMDS V1.1 and V1.3 compliant
• Supports 16, 64 and 256QAM
• Supports 16, 64 and 256 TCM
• Internal 8-bit ADC
• Interface for 10-bit external ADC
• 36.125MHz nominal IF input
• Symbol rate range 5 – 5.304Mbaud in 6MHz
channels
• Integrated matched filtering with 0.15 roll-off factor
• ±400KHz internal carrier offset compensation with
negligible losses @ 5Mbaud 6MHz channel
• Symbol timing loop designed to acquire with large
offsets. Negligible losses for ±100ppm offsets
100 pin QFP (Plastic)
• All internal clocks derived from single fixed
frequency crystal (30MHz)
• Supports fast re-acquisition mode
• 6µs echo cancellation @ 5Mbaud
• Constellation points and equalizer tap values
readable via I2C bus
• C/N estimation readable via I2C bus
• Low implementation loss for AWGN only:
0.5dB @ 64QAM (using internal 8-bit A/D);
0.3dB @ 256QAM (excluding A/D);
measured at BER of 3x10–4 Pre R/S
• I = 12 and I = 204 de-interleaving
• Fast I2C bus compatible control interface
• Tuner IF-AGC output
• User programmable tuner RF-AGC output
• Dedicated 3-wire bus interface to configure up to 2
tuner synthesizers
• 3.3V CMOS technology
• Supports JTAG boundary scan
• 100-pin QFP package
Applications
MMDS set-top boxes
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
PE99906-PS
1 page  
CXD1958Q
Name
Pin No.
Type
Tuner Interface (Control and AGC) (Cont.)
SCLK
44
Digital
open-drain output
SDATA
45
Digital
open-drain output
Host Control Interface
SDA
48
SCL 49
A1 97
A0 98
Digital
bi-directional
open-drain output
Schmitt trigger
5V tolerant input
Digital
Schmitt trigger
5V tolerant input
Digital
CMOS input
Digital
CMOS input
INTRPTN
41
Digital
open-drain output
Testability and Evaluation Interface
DT[9:0]
63, 62, 61,
60, 59, 56,
55, 54, 53,
52
Digital
bi-directional
tristate output
5V tolerant input
DTCLK
87
Digital
output
TRST
93
Digital
input with pull-up
TDO
15
Digital
tristate output
TDI
94
Digital
input with pull-up
TMS
95
Digital
input with pull-up
TCK
96
Digital
input
TEVAL[9:0]
1, 2, 3, 4,
5, 8, 9, 10,
11, 12
Digital
output
Drive
Function
12mA
12mA
3-wire bus interface clock output. Must
be pulled up by external resistor to 3.3V
or 5V if used.
3-wire bus interface data output. Must
be pulled up by external resistor to 3.3V
or 5V if used.
3mA
I2C bus data. Must be pulled up by
external resistor.
N/A
N/A
N/A
12mA
I2C bus clock. Must be pulled up by
external resistor.
I2C bus address (variable part)
I2C bus address (variable part)
Programmable general interrupt pin.
Must be pulled up by external resistor to
3.3V or 5V.
IOL = 4mA ADC digital bypass port for connection
IOH = –2mA of an external ADC.
8mA
N/A
4mA
N/A
N/A
N/A
ADC clock for use with DT[9:0].
JTAG test reset input.
JTAG test data output.
JTAG test data input.
JTAG test mode select.
JTAG test clock.
4mA
Test data bus.
–5–
5 Page 
CXD1958Q
3-6. Energy Dispersal De-randomiser
The error-corrected bytes are de-randomized with a 15-stage PRBS (Pseudo Random Binary Sequence)
generator, with polynomial 1 + X14 + X15 and start-up sequence “100101010000000”. Sync bytes are not de-
scrambled, and when an inverted sync byte is detected, every 8th packet, the PRBS resets to the start-up
sequence and the sync byte is re-inverted. The de-scrambled data is output through the TSDATA pins, along
with a data clock and synchronization signal.
3-7. BER Calculation
In addition to the above functionality, the postprocessor includes comprehensive signal quality measurement
logic. The Bit Error Rate (BER) of the received signal (before and after R/S correction) and a measure of the
long-term signal quality are available via I2C bus registers. The calculated Bit Error Rate (BER) of the received
signal is accurate for pre R/S BER figures better than 1 × 10–3.
3-8. MPEG2 Baseband Interface
Fig. 5 illustrates the relationship between the CXD1958Q MPEG2 transport stream interface signals. The
transport stream clock (TSCLK) can be programmed for the external device to sample on the rising or falling
edge (only rising edge sampling is shown here). The interface supports a number of additional signals, which
indicate the integrity of the output data. Once the demodulator has achieved lock to the MPEG2 sync byte, the
transport stream interface is activated. Fig. 5 shows a complete MPEG2 packet consisting of a sync byte (47h)
data bytes (dd) and Reed Solomon bytes (rr). Note that all the interface control signals have individual
programmable polarity; active high signals are shown in the diagram.
TSCLK has two operating modes selected via I2C bus:
• Whole Packet Mode, where the clock is activated for all 204 bytes of the packet, requiring the external
interface to use TSVALID to distinguish between data and 16 Reed Solomon bytes.
• Data Only Mode, where the clock is activated only for each of the 188 sync and data bytes, and remains
inactive during the 16 Reed Solomon bytes.
TSDATA[7:0] is the byte wide MPEG2-TS data with programmable MSB/LSB ordering. The default is
TSDATA7 being the MSB.
TSVALID has two operating modes selected via I2C bus:
• Data Only Mode: where TSVALID is set active during the 188 byte data portion of the packet, and reset
inactive during the 16 Reed Solomon bytes. It is used by the external device as a clock enable to qualify
when data is valid on TSDATA[7:0].
• Pulsed Mode: where TSVALID is set active during the MPEG2 sync byte and reset inactive for the remainder
of the packet, and thus becomes equivalent to a sync byte indicator.
TSSYNC is set active during the MPEG2 sync byte and reset inactive for the remainder of the packet.
TSERR is only set active if the Transport Stream Error flag is set. This signal indicates that the Reed Solomon
decoder was unable to correct all errors in the packet. There are 3 programmable modes for this signal:
• Whole Packet Mode: Active during the entire 204-byte packet
• Data Only Mode: Active during the 188 byte data portion of packet and inactive during the 16 Reed Solomon
bytes
• Pulsed Mode: Pulsed active during sync byte period only
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD1958Q.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CXD1958Q | MMDS TCM/QAM Demodulator + FEC + ADC | Sony Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |