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PDF CXD1915R Data sheet ( Hoja de datos )
| Número de pieza | CXD1915R | |
| Descripción | Digital Video Encoder | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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Digital Video Encoder
CXD1915R
Description
The CXD1915R is a digital video encoder designed
for DVDs, set top boxes, digital VCRs and other
digital video equipment. This device accepts ITU-
R601 format Y, Cb and Cr data and ITU-R656 format
Y, Cb and Cr data, and the data are encoded to
composite video and separate Y/C video (S-video)
signals and converted to RGB/YUV signals.
80 pin LQFP (Plastic)
Features
• NTSC, PAL, MPAL and 4.43NTSC encoding modes
• Composite video and separate Y/C video (S-video)
signal output
• R, G, B/Y, U, V (BetaCam/SMPTE level) signal
output
• 8/16-bit pixel data input modes
• 13.5Mpps pixel rate
• 12.27 and 14.75Mpps square pixel rates
• External synchronization using HSYNC, VSYNC
and FID inputs, or internal synchronization
• Supports interlace and non-interlace modes
• On-chip 100% color bar generator
• OSD function
• ITU-R656 code signal EAV decoding
• Supports I2C bus (400kHz) and Sony SIO
• Closed Caption (line 21, line 284) encoding
• VBID encoding
• WSS encoding
• 10-bit 6-channel DAC
• Macrovision Pay-Per-View copy protection system
Rev. 7.1.L1∗1
• Monolithic CMOS single 3.3V power supply
• 80-pin plastic LQFP
Absolute Maximum Ratings
• Supply voltage
VDD VSS – 0.5 to +4.6 V
• Input voltage
VI VSS – 0.5 to +7.0 V
• Output voltage
VO VSS – 0.5 to VDD + 0.5 V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg –55 to +150 °C
(VSS = 0V)
Recommended Operating Conditions
• Supply voltage
VDD
3.3 ± 0.3
• Input voltage VIN VSS to 5.5
• Operating temperature
Topr
0 to +70
V
V
°C
I/O Capacitance
• Input capacitance CI
• Output capacitance CO
9 (Max.)
11 (Max.)
pF
pF
Note) Test conditions: VDD = VI = 0V, fM = 1MHz
∗1 This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of
the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial home use only. Reverse
engineering or disassembly is prohibited.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99422-PS
1 page  
CXD1915R
Pin
No.
Symbol
46 AVDD1
47 AVSS1
48 C-OUT
49 VB
50 VG
51 Y-OUT
52 AVDD2
53 AVSS2
54 B-OUT
55 AVSS4
56 G-OUT
57 AVDD3
58 AVSS3
59 R-OUT
60 VSS8
61 TVSYNC
62 TD8
63 TD9
64 TD10
65 VDD4
66 XTEST
67
OSDSW/
XTEST1
68
ROSD/
XTEST2
69
GOSD/
XTEST3
70
BOSD/
XTEST4
71 XTEST5
72 SYNCM
73 PIXCON
74 VSS9
75 TDI
I/O Description
— Analog power supply.
— Analog ground.
O 10-bit DAC output. This pin outputs the chroma (C) signal.
O Connect to ground via a capacitor of approximately 0.1µF.
O Connect to analog power supply via a capacitor of approximately 0.1µF.
O 10-bit DAC output. This pin outputs the luminance (Y) signal.
— Analog power supply.
— Analog ground.
O 10-bit DAC output. This pin outputs the B and U signals.
— Analog ground.
O 10-bit DAC output. This pin outputs the G and Y signals.
— Analog power supply.
— Analog ground.
O 10-bit DAC output. This pin outputs the R and V signals.
— Digital ground.
I Test pin. This pin is pulled up. Normally this pin should be open.
I/O Test data inputs/outputs. These pins should be open.
I/O In test mode, these are used for the internal circuit test data bus.
I/O The test data bus is available only for the device vendor.
— Digital power supply.
I
Test mode control. This pin is pulled up.
Normally this pin should be open.
I
These pins are pulled up. The functions of these pins are selected by XTEST
I (Pin 66).
When XTEST = High, these are OSD data inputs.
I When XTEST = Low, these are test mode control inputs.
The test mode is available only for the device vendor.
I
I Test pin. This pin is pulled up. Normally this pin should be open.
Master/slave switching. This pin is pulled up.
I When SYNCM = High, the CXD1915R is set to master mode.
When SYNCM = Low, the CXD1915R is set to slave mode.
I
Control register bit "PIX_EN" default value control.
This pin is pulled up.
— Digital ground.
I Test mode control input. This pin is pulled up.
–5–
5 Page 
CXD1915R
4. SYSCLK, PDCLK, BF, CSYNC, HSYNC, VSYNC, FID
SYSCLK
PDCLK
VSYNC∗1
HSYNC∗1
FID∗1
CSYNC
BF
fSYSCLK
tPWHCLK
tPWLCLK
tPDCLKD
tCOD
tCOH
tPDCLKD
∗1 In master mode
Item
SYSCLK clock rate
SYSCLK pulse width Low
SYSCLK pulse width High
PDCLK delay time from SYSCLK
Control output delay time from SYSCLK
Control output hold time from SYSCLK
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Symbol
fSYSCLK
tPWLCLK
tPWHCLK
tPDCLKD∗
tCOD∗
tCOH∗
Min.
11
11
3
Typ.
27
Max. Unit
MHz
ns
ns
20 ns
26 ns
ns
∗ CL = 35pF
5. 8-bit mode
(1) Pixel data interface
SYSCLK
PD0 to PD7
tPDS
tPDH
Item
Pixel data setup time to SYSCLK
Pixel data hold time to SYSCLK
(Ta = 0 to +70°C, VDD = 3.3 ± 0.3V, Vss = 0V)
Symbol
tPDS
tPDH
Min.
11
0
– 11 –
Typ.
Max.
Unit
ns
ns
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD1915R.PDF ] | |
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