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PDF CXD1198AQ Data sheet ( Hoja de datos )
| Número de pieza | CXD1198AQ | |
| Descripción | CD-ROM Subcode Decoder | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD1198AQ
CD-ROM Subcode Decoder
For the availability of this product, please contact the sales office.
Description
The CXD1198AQ is a CD-ROM subcode decoder
100 pin QFP (Plastic)
LSI.
Features
• Real time error correction of subcodes
• Connection possible with DRAM up to 1 MB as
buffer memory
• Automatic generation of sync patterns
• Error pointer buffering function (separated mode,
mixed mode)
• 4 MB/s maximum rate for transferring data with
SCSI control LSI
Applications
CD-ROM drives
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
VCC –0.5 to +7.0 V
• Input voltage
VI –0.5 to VDD +0.5 V
• Output voltage
VO –0.5 to VDD +0.5 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage
VDD 5.0±0.5
• Operating temperature Topr –20 to +75
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E92632A78-TE
1 page  
CXD1198AQ
Pin No.
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
XHCS
HA0
HA1
HINT
HINP
NC1
NC2
XDAC
DDRQ
XDRS
VDD
VSS
DDBP
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
XDWR
VSS
XDRD
XDCS
DA1
DA0
A5
A4
A3
A2
A1
A0
I/O Description
I Chip select input signal from host
I Host address signal
I Host address signal
O Interrupt request signal to host
I HINT signal polarity control input signal
O No connection; leave open.
O No connection; leave open.
O DMA acknowledge negative logic signal to the CXD1186BQ
I Data request positive logic signal from the CXD1186BQ
O Reset negative logic signal to the CXD1186BQ
Power supply (+5 V)
GND
I/O Error pointer bus connected with the CXD1186BQ
I/O Data bus connected with the CXD1186BQ
I/O Data bus connected with the CXD1186BQ
I/O Data bus connected with the CXD1186BQ
I/O Data bus connected with the CXD1186BQ
I/O Data bus connected with the CXD1186BQ
I/O Data bus connected with the CXD1186BQ
I/O Data bus connected with the CXD1186BQ
I/O Data bus connected with the CXD1186BQ
O Host register write strobe negative logic signal to the CXD1186BQ
GND
O Host register read strobe negative logic signal to the CXD1186BQ
Chip select negative logic signal for host register read/write to the
O
CXD1186BQ
O Address signal to the CXD1186BQ
O Address signal to the CXD1186BQ
I CPU address signal
I CPU address signal
I CPU address signal
I CPU address signal
I CPU address signal
I CPU address signal
—5—
5 Page 
CXD1198AQ
5. Host DMA cycle (SCSI bus)
(1) Read
SDRQ
XSAC
XHRD
tDDA
tDAR
HDB0 to 7
Item
XSAC fall time (vs. SDRQ↓)
HDRQ cycle time (vs. XSAC↑)
XHRD delay time (vs. XSAC↑)
XSAC delay time (vs. XHRD↑)
Low-level XHRD pulse width
Data setup time (vs. XHRD↑)
Data hold time (vs. XHRD↑)
TW is 1/f here.
tRRL
tSRD
tDRA
tHRD
tDARS
Symbol
tDDA
tDARS
tDAR
tDRA
tRRL
tSRD
tHRD
Min.
15
5
Typ.
0
23
2TW
Max.
TW+31
TW
Unit
ns
ns
ns
ns
ns
ns
ns
(2) Write
SDRQ
XSAC
XHWR
tDDA
tDAW
HDB0 to 7
Item
XSAC fall time (vs. SDRQ↓)
SDRQ rise time (vs. XSAC↑)
XHWR delay time (vs. XSAC↓)
XSAC delay time (vs. XHWR↑)
Low-level XHWR pulse width
Data delay time (vs. XHWR↓)
Data float time (vs. XHWR↑)
TW is 1/f here.
tWWL
tDWD
tDWA
tFWD
tDARS
Symbol
tDDA
tDARS
tDAW
tDWA
tWWL
tDWD
tFWD
Min.
10
Typ.
24
2TW
Max.
TW+31
TW
0
38
Unit
ns
ns
ns
ns
ns
ns
ns
—11—
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD1198AQ.PDF ] | |
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