PDF CXD1186CQ Data sheet ( Hoja de datos )

Número de pieza	CXD1186CQ
Descripción	CD-ROM Decoder
Fabricantes	Sony Corporation
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No Preview Available ! CXD1186CQ/CR CD-ROM Decoder For the availability of this product, please contact the sales office. Description The CXD1186C is a CD-ROM decoder LSI. CXD1186CQ 80 pin QFP (Plastic) CXD1186CR 80 pin LQFP (Plastic) Features • Corresponds to CD-ROM, CD-I and CD-ROM XA formats. • Real time error correction. (Erasure correction using C2 pointer from CD player.) • Double speed playback. • Connection to standard SRAM up to 64 K bytes, as buffer memory, possible. Applications CD-ROM driver Structure Silicon gate CMOS IC Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VDD –0.5 to +7.0 V • Input voltage VI –0.5 to VDD +0.5 V • Output voltage VO –0.5 to VDD +0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD +4.5 to +5.5 V (standard +5.0) • Operating temperature Topr –20 to +75 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E93512A78-TE 1 page CXD1186CQ/CR Pin No. CXD1186CQ CXD1186CR 40 38 41 39 42 40 43 41 44 42 45 43 46 44 47 45 48 46 49 47 50 48 51 49 52 50 53 51 54 52 55 53 56 54 57 55 58 56 59 57 60 58 61 59 62 60 63 61 64 62 65 63 66 64 67 65 68 66 69 67 70 68 71 69 72 70 73 71 74 72 75 73 76 74 77 75 78 76 Symbol BA8 BA9 GND BA10 BA11 BA12 BA13 BA14 BA15 XMOE XMWR BDB0 GND BDB1 BDB2 BDB3 BDB4 BDB5 BDB6 BDB7 BDBP XTL2 XTL1 GND HCLK LRCK DATA BCLK C2PO DB0 DB1 DB2 DB3 VDD DB4 DB5 DB6 DB7 XCS 79 77 XRD 80 78 XWR I/O Description O Buffer memory address O Buffer memory address — GND pin O Buffer memory address O Buffer memory address O Buffer memory address O Buffer memory address O Buffer memory address O Buffer memory address O Buffer memory output enable negative logic signal O Buffer memory write negative logic signal I/O Buffer memory data bus — GND pin I/O Buffer memory data bus I/O Buffer memory data bus I/O Buffer memory data bus I/O Buffer memory data bus I/O Buffer memory data bus I/O Buffer memory data bus I/O Buffer memory data bus I/O Buffer memory pointer data bus O Crystal oscillation circuit output pin I Crystal oscillation circuit input pin — GND pin O 1/2 frequency divided clock signal of XTL1 I LR clock from CD player I Serial data from CD player I Bit clock from CD player I C2 pointer from CD player I/O CPU data bus I/O CPU data bus I/O CPU data bus I/O CPU data bus — Power (+5 V) supply pin I/O CPU data bus I/O CPU data bus I/O CPU data bus I/O CPU data bus I Chip select negative logic signal from CPU CPU strobe negative logic signal to read out this IC internal I register CPU strobe negative logic signal to write in this IC internal I register —5— 5 Page 5. HOST DMA cycle (SCSI bus) (1) Read CXD1186CQ/CR SDRQ XSAC XHRD HDB0 to 7, P tDDA tDAR tRRL tDRD tDRA tHRD Item XSAC fall time (vs. SDRQ ↑) XSAC delay time (vs. XHRD ↓) XSAC delay time (vs. XHRD ↑) Low level XHRD pulse width Data delay time (vs. XHRD ↓) Data hold time (vs. XHRD ↑) Symbol tDDA tDAR tDRA tRRL tDRD tHRD Min. 0 T+59 0 Typ. Max. Tw Tw 90 Unit n n n n n n (2) Write SDRQ XSAC XHWR HDB0 to 7, P tDDA tDAW tWWL tDWA tSDW tFWD Item XSAC fall time (vs. SDRQ ↑) XHWR delay time (vs. XSAC ↓) XSAC delay time (vs. XHWR ↑) Low level XHWR pulse width Data setup time (vs. XHWR ↓) Data float time (vs. XHWR ↓) Where T in the chart indicates : Tw for 3 cycle mode 2 • Tw for 4 cycle mode 3 • Tw for 5 cycle mode Here Tw=1/f Symbol tDDA tDAW tDWA tWWL tSDW tFWD Min. T T+24 27 Typ. Max. Tw Tw Tw Unit n n n n n n —11— 11 Page

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