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100324F PDF даташит

Спецификация 100324F изготовлена ​​​​«National Semiconductor» и имеет функцию, называемую «Low Power Hex TTL-to-ECL Translator».

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Номер произв 100324F
Описание Low Power Hex TTL-to-ECL Translator
Производители National Semiconductor
логотип National Semiconductor логотип 

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100324F Даташит, Описание, Даташиты
August 1998
100324
Low Power Hex TTL-to-ECL Translator
General Description
The 100324 is a hex translator, designed to convert TTL
logic levels to 100K ECL logic levels. The inputs are compat-
ible with standard or Schottky TTL. A common Enable (E),
when LOW, holds all inverting outputs HIGH and holds all
true outputs LOW. The differential outputs allow each circuit
to be used as an inverting/non-inverting translator, or as a
differential line driver. The output levels are voltage compen-
sated over the full −4.2V to −5.7V range.
When the circuit is used in the differential mode, the 100324,
due to its high common mode rejection, overcomes voltage
gradients between the TTL and ECL ground systems. The
VEE and VTTL power may be applied in either order.
The 100324 is pin and function compatible with the 100124
with similar AC performance, but features power dissipation
roughly half of the 100124 to ease system cooling require-
ments.
Features
n Pin/function compatible with 100124
n Meets 100124 AC specifications
n 50% power reduction of the 100124
n Differential outputs
n 2000V ESD protection
n −4.2V to −5.7V operating range
n Standard Microcircuit Drawing
(SMD) 5962-9153001
Logic Diagram
Pin Names
D0– D5
E
Q0– Q5
Q0– Q5
Description
Data Inputs
Enable Input
Data Outputs
Complementary
Data Outputs
DS100313-4
© 1998 National Semiconductor Corporation DS100313
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100324F Даташит, Описание, Даташиты
Connection Diagrams
24-Pin DIP
DS100313-1
24-Pin Quad Cerpak
DS100313-2
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100324F Даташит, Описание, Даташиты
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Above which the useful life may be impaired.
Storage Temperature (TSTG)
Maximum Junction Temperature (TJ)
Ceramic
−65˚C to +150˚C
+175˚C
VEE Pin Potential to Ground Pin
VTTL Pin Potential to Ground Pin
Input Voltage (DC)
−7.0V to +0.5V
−0.5V to +6.0V
−0.5V to +6.0V
Output Current (DC Output HIGH)
−50 mA
ESD (Note 2)
2000V
Recommended Operating
Conditions
Case Temperature (TC)
Military
−55˚C to +125˚C
Supply Voltage (VEE)
−5.7V to −4.2V
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C, VTTL = +4.5V to +5.5V
Symbol
Parameter
Min Max Units
TC
Conditions
VOH
Output HIGH Voltage
−1025
−1085
−870
−870
mV
mV
0˚C to +125˚C
−55˚C
VIN = VIH (Max)
or VIL (Min)
Loading with
50to −2.0V
Notes
(Notes 3, 4, 5)
VOL
VOHC
Output LOW Voltage
Output HIGH Voltage
−1830
−1830
−1035
−1085
−1620
−1555
mV
mV
mV
mV
0˚C to +125˚C
−55˚C
0˚C to +125˚C
−55˚C
VIN = VIH (Max)
or VIL (Min)
Loading with
50to −2.0V
(Notes 3, 4, 5)
VOLC
Output LOW Voltage
−1610
−1555
mV
mV
0˚C to +125˚C
−55˚C
VIH
VIL
IIH
IIL
VFCD
IEE
ITTL
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Breakdown Test
Input LOW Current
Data
Enable
Input Clamp Diode Voltage
VEE Power Supply Current
VTTL Power Supply Current
2.0 5.0
V
0.0 0.8
V
20 µA
100 µA
−0.9
−5.4
−70
−1.2
−22
38
mA
V
mA
mA
−55˚C to +125˚C
−55˚C to +125˚C
−55˚C to +125˚C
−55˚C to +125˚C
−55˚C to +125˚C
−55˚C to +125˚C
−55˚C to +125˚C
−55˚C to +125˚C
Over VTTL, VEE, TC Range
Over VTTL, VEE, TC Range
VIN = +2.7V
VIN = +7.0V
VIN = +0.4V
IIN = −18 mA
All Inputs VIN = +4.0V
All Inputs VIN = GND
(Notes 3, 4, 5, 6)
(Notes 3, 4, 5, 6)
(Notes 3, 4, 5)
(Notes 3, 4, 5)
(Notes 3, 4, 5)
(Notes 3, 4, 5)
(Notes 3, 4, 5)
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 4: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8.
Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8.
Note 6: Guaranteed by applying specified input condition and testing VOH/VOL.
AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND, VTTL = +4.5V to +5.5V
Symbol
Parameter
TC = −55˚C
TC = +25˚C
Min Max Min Max
TC = +125˚C
Min Max
Units
Conditions
Notes
tPLH
tPHL
tTLH
tTHL
Propagation Delay
Data and Enable to Output
Transition Time
20% to 80%, 80% to 20%
0.50 3.00 0.50 2.90 0.30 3.30
0.35 1.80 0.45 1.80 0.45 1.80
ns
ns
Figures 1, 2
(Notes 7, 8, 9)
(Note 10)
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures.
Note 8: Screen tested 100% on each device at +25˚C temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, Subgroups A10 and A11.
Note 10: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data).
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