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PDF CY7C68000-56PVC Data sheet ( Hoja de datos )
| Número de pieza | CY7C68000-56PVC | |
| Descripción | TX2 USB 2.0 UTMI Transceiver | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CY7C68000
TX2™ USB 2.0 UTMI Transceiver
1.0 EZ-USB TX2 Features
• Synchronous field and EOP detection on receive pack-
The Cypress EZ-USB TX2 is a Universal Serial Bus (USB)
specification revision 2.0 transceiver, serial/deserializer, to a
parallel interface of either 16 bits at 30 MHz or eight bits at 60
MHz. The TX2 provides a high-speed physical layer interface
ets
• Synchronous field and EOP generation on transmit
packets
• Data and clock recovery from the USB serial stream
that operates at the maximum allowable USB 2.0 bandwidth. • Bit stuffing/unstuffing; bit stuff error detection
This allows the system designer to keep the complex high-
speed analog USB components external to the digital ASIC
which decreases development time and associated risk. A
standard interface is provided that is USB 2.0-certified and is
compliant with Transceiver Macrocell Interface (UTMI) speci-
fication version 1.05 dated 3/29/01.
• Staging register to manage data rate variation due to
bit stuffing/unstuffing
• 16-bit 30-MHz, and 8-bit 60-MHz parallel interface
• Ability to switch between FS and HS terminations and
signaling
Two packages are defined for the family: 56-pin SSOP and 56-
pin QFN.
The function block diagram is shown in Figure 1-1.
• UTMI-compliant/USB-2.0-certified for device operation
• Operates in both USB 2.0 high speed (HS), 480
Mbits/second, and full speed (FS), 12 Mbits/second
• Supports detection of USB reset, suspend, and resume
• Supports HS identification and detection as defined by
the USB 2.0 Specification
• Supports transmission of resume signaling
• 3.3V operation
• Two package options—56-pin QFN, and 56-pin SSOP
• Serial-to-parallel and parallel-to-serial conversions
• All required terminations, including 1.5K-ohm pull-up
• 8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirec-
on DPLUS, are internal to chip
tional external data interface
• Supports USB 2.0 test modes.
CY7C68000
CY7C68000
XTALIN/
OUT
OSC
20X
PLL
PLL_480
UTMI CLK
UTMI CLK
Full-Speed Rx
High-Speed Rx Traffic
USB
Sync
USB 2.0
XCVR High-Speed Tx
Full-Speed Tx
Elasticity
Buffer
Fast
Digital
Rx
Fast
Digital
Tx
Digital
Rx
Digital
Tx
UTMI Rx Ctl
UTMI Rx Data 8/16
BIDI Option
Also
UTMI Rx Data 8/16
UTMI Tx Ctl
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation
Document #: 38-08016 Rev. *E
• 3901 North First Street
• San Jose, CA 95134 • 408-943-2600
Revised November 2, 2004
1 page  
PRELIMINARY
CY7C68000
Table 5-1. Pin Descriptions (continued)[1]
SSOP QFN
Name
56 49 D0
55 48 D1
53 46 D2
51 44 D3
50 43 D4
48 41 D5
46 39 D6
45 38 D7
44 37 D8
43 36 D9
41 34 D10
40 33 D11
38 31 D12
36 29 D13
34 27 D14
33 26 D15
1 50 CLK
10 3 Reset
19 12 XcvrSelect
20 13 TermSelect
9 2 Suspend
26 19 LineState1
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Output
Input
Input
Input
Input
Output
Default
Description
Bidirectional Data Bus. This bidirectional bus is used as the entire data
bus in the 8-bit bidirectional mode or the least significant eight bits in the 16-
bit mode or under the 8 bit uni-directional mode these bits are used as inputs
for data, selected by the RxValid signal.
Bidirectional Data Bus. This bidirectional bus is used as the upper eight
bits of the data bus when in the 16-bit mode, and not used when in the 8-bit
bidirectional mode. Under the 8 bit uni-directional mode these bits are used
as outputs for data, selected by the TxValid signal.
Clock. This output is used for clocking the receive and transmit parallel data
on the D[15:0] bus.
N/A Active HIGH Reset. Resets the entire chip. This pin can be tied to VCC
through a 0.1-µF capacitor and to GND through a 100K resistor for a 10
msec RC time constant.
N/A Transceiver Select. This signal selects between the Full Speed (FS) and
the High Speed (HS) transceivers:
0: HS transceiver enabled
1: FS transceiver enabled
N/A Termination Select. This signal selects between the between the Full
Speed (FS) and the High Speed (HS) terminations:
0: HS termination
1: FS termination
N/A Suspend. Places the CY7C68000 in a mode that draws minimal power from
supplies. Shuts down all blocks not necessary for Suspend/Resume opera-
tions. While suspended, TermSelect must always be in FS mode to ensure
that the 1.5 K ohm pull-up on DPLUS remains powered.
0: CY7C68000 circuitry drawing suspend current
1: CY7C68000 circuitry drawing normal current
Line State. These signals reflect the current state of the single-ended
receivers. They are combinatorial until a “usable” CLK is available then they
are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D- D+ Description
0 0 0: SE0
0 1 1: ‘J’ State
1 0 2: ‘K’ State
1 1 3: SE1
Document #: 38-08016 Rev. *E
Page 5 of 14
5 Page 
10.0 Ordering Information
Table 10-1. Ordering Information
Ordering Code
CY7C68000-56LFC
CY7C68000-56PVC
CY7C68000-56PVCT
CY3683
11.0 Package Diagrams
The TX2 is available in two packages:
• 56-pin SSOP
• 56-pin QFN.
PRELIMINARY
CY7C68000
Package Type
56 QFN
56 SSOP
56 SSOP Tape/Reel
EZ-USB TX2 Development Board
Figure 11-1. 56-lead Shrunk Small Outline Package O56
51-85062-*C
Document #: 38-08016 Rev. *E
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY7C68000-56PVC.PDF ] | |
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