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PDF LTC1591IN Data sheet ( Hoja de datos )

Número de pieza LTC1591IN
Descripción 14-Bit and 16-Bit Parallel Low Glitch Multiplying DACs with 4-Quadrant Resistors
Fabricantes Linear Technology 
Logotipo Linear Technology Logotipo



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LTC1591/LTC1597
FEATURES
14-Bit and 16-Bit Parallel
Low Glitch Multiplying DACs
with 4-Quadrant Resistors
DESCRIPTION
s True 16-Bit Performance Over Industrial
Temperature Range
s DNL and INL: 1LSB Max
s On-Chip 4-Quadrant Resistors Allow Precise 0V to
10V, 0V to – 10V or ±10V Outputs
s Pin Compatible 14- and 16-Bit Parts
s Asynchronous Clear Pin
LTC1591/LTC1597: Reset to Zero Scale
LTC1591-1/LTC1597-1: Reset to Midscale
s Glitch Impulse < 2nV-s
s 28-Lead SSOP Package
s Low Power Consumption: 10µW Typ
s Power-On Reset
U
APPLICATIONS
s Process Control and Industrial Automation
s Direct Digital Waveform Generation
s Software-Controlled Gain Adjustment
s Automatic Test Equipment
The LTC®1591/LTC1597 are pin compatible, parallel input
14-bit and 16-bit multiplying current output DACs that oper-
ate from a single 5V supply. INL and DNL are accurate to 1LSB
over the industrial temperature range in both 2- and 4-
quadrant multiplying modes. True 16-bit 4-quadrant multi-
plication is achieved with on-chip 4-quadrant multiplication
resistors.
These DACs include an internal deglitcher circuit that reduces
the glitch impulse to less than 2nV-s (typ). The asynchronous
CLR pin resets the LTC1591/LTC1597 to zero scale and
LTC1591-1/LTC1597-1 to midscale.
The LTC1591/LTC1597 are available in 28-pin SSOP and
PDIP packages and are specified over the industrial tempera-
ture range.
For serial interface 16-bit current output DACs refer to the
LTC1595/LTC1596 data sheet.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
16-Bit, 4-Quadrant Multiplying DAC with a
Minimum of External Components
VREF
+ 5V
LT®1468
0.1µF
15pF
32
R1 RCOM
1 23 4
REF VCC ROFS
5
RFB
16
DATA
INPUTS
R1 R2
LTC1597-1
ROFS RFB
16-BIT DAC
IOUT1 6
AGND 7
10 TO 21,
24 TO 27
WR LD CLR
WR 9 8 28
LD
CLR
22
DGND
15pF
LT1468
+
VOUT =
–VREF
TO VREF
1591/97 TA01
LTC1591/LTC1591-1 Integral Nonlinearity
1.0
0.8
VREF = 10V
VOUT = ±10V BIPOLAR
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
4096
8192 12288 16383
DIGITAL INPUT CODE
1591/97 TA02
LTC1597/LTC1597-1 Integral Nonlinearity
1.0
0.8
VREF = 10V
VOUT = ±10V BIPOLAR
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384 32768 49152
DIGITAL INPUT CODE
65535
1591/97 TA03
1

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LTC1591IN pdf
LTC1591/LTC1597
TYPICAL PERFOR A CE CHARACTERISTICS (LTC1591/LTC1597)
Midscale Glitch Impulse
40
USING AN LT1468
30 CFEEDBACK = 30pF
VREF = 10V
20
10
0
1nV-s TYPICAL
– 10
– 20
– 30
– 40
0
0.2 0.4 0.6 0.8 1.0
TIME (µs)
1591/97 G01
Full-Scale Settling Waveform
LD PULSE
5V/DIV
GATED
SETTLING
WAVEFORM
500µV/DIV
500ns/DIV
USING LT1468 OP AMP
CFEEDBACK = 20pF
0V to 10V STEP
1591/97 G02
Unipolar Multiplying Mode
Signal-to-(Noise + Distortion)
vs Frequency
– 40
VCC = 5V USING AN LT1468
– 50
CFEEDBACK = 30pF
REFERENCE = 6VRMS
– 60
– 70
– 80
– 90
– 100
– 110
10
500kHz FILTER
80kHz FILTER
30kHz FILTER
100 1k 10k
FREQUENCY (Hz)
100k
1591/97 G03
Bipolar Multiplying Mode
Signal-to-(Noise + Distortion)
vs Frequency, Code = All Zeros
– 40
VCC = 5V USING TWO LT1468s
– 50
CFEEDBACK = 15pF
REFERENCE = 6VRMS
– 60
Bipolar Multiplying Mode
Signal-to-(Noise + Distortion)
vs Frequency, Code = All Ones
– 40
VCC = 5V USING TWO LT1468s
– 50
CFEEDBACK = 15pF
REFERENCE = 6VRMS
– 60
– 70 – 70
– 80
– 90
– 100
– 110
10
500kHz FILTER
80kHz FILTER
30kHz
FILTER
100 1k 10k
FREQUENCY (Hz)
100k
1591/97 G04
– 80
– 90
– 100
– 110
10
500kHz FILTER
80kHz FILTER
30kHz FILTER
100 1k 10k
FREQUENCY (Hz)
100k
1591/97 G05
Supply Current vs Input Voltage
5
VCC = 5V
ALL DIGITAL INPUTS
TIED TOGETHER
4
3
2
1
Logic Threshold vs Supply Voltage
3.0
2.5
2.0
1.5
1.0
0.5
0
01 2 345
INTPUT VOLTAGE (V)
1591/97 G06
0
01234567
SUPPLY VOLTAGE (V)
1591/97 G07
5

5 Page





LTC1591IN arduino
LTC1591/LTC1597
TRUTH TABLE
Table 1
CONTROL INPUTS
CLR WR LD
0XX
100
111
101
1
110
REGISTER OPERATION
Reset Input and DAC Register to All 0s for LTC1591/LTC1597 and Midscale for LTC1591-1/LTC1597-1 (Asynchronous Operation)
Load Input Register with All 14/16 Data Bits
Load DAC Register with the Contents of the Input Register
Input and DAC Register Are Transparent
CLK = LD and WR Tied Together. The 14/16 Data Bits Are Loaded into the Input Register on the Falling Edge of the CLK and Then
Loaded into the DAC Register on the Rising Edge of the CLK
No Register Operation
BLOCK DIAGRA SM
REF 1
12k
48k 48k 48k
RCOM 2
12k
R1 3
LTC1591
48k 48k 48k 48k
48k 48k
5 RFB
96k 96k
12k
96k 96k 12k
4 ROFS
VCC 23
LD 8
DECODER
D13
LOAD (MSB)
D12
D11 D10
DAC REGISTER
D9 • • •
D0
(LSB) RST
6 IOUT1
7 AGND
22 DGND
28 CLR
WR 9
WR
10 11
D13 D12
INPUT REGISTER
RST
••••
21 24 25 26 27
D2 D1 D0 NC NC
1591 BD
11

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