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PDF CS8413-CS Data sheet ( Hoja de datos )
| Número de pieza | CS8413-CS | |
| Descripción | 96 KHZ DIGITAL AUDIO RECEIVER | |
| Fabricantes | ETC | |
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CS8413
CS8414
96 kHz Digital Audio Receiver
Features
l Sample Rates to >100 kHz
l Low-Jitter, On-Chip Clock Recovery
256xFs Output clock Provided
l Supports: AES/EBU, IEC 958, S/PDIF, &
EIAJ CP340/1201 Professional and
Consumer Formats
l Extensive Error Reporting
Repeat Last Sample on Error Option
l On-Chip RS422 Line Receiver
l Configurable Buffer Memory (CS8413)
l Pin Compatible with CS8411 and CS8412
Description
The CS8413 and CS8414 are monolithic CMOS devices
which receive and decode audio data up to 96kHz ac-
cording to the AES/EBU, IEC958, S/PDIF, and EIAJ
CP340/1201 interface standards. The CS8413 and
CS8414 receive data from a transmission line, recover
the clock and synchronization signals, and de-multiplex
the audio and digital data. Differential or single ended in-
puts can be decoded.
The CS8413 has a configurable internal buffer memory,
read through a parallel port, which may be used to buffer
channel status, auxiliary data, and/or user data.
The CS8414 de-multiplexes the channel, user, and va-
lidity data directly to serial output pins with dedicated
output pins for the most important channel status bits.
ORDERING INFORMATION
CS8413-CS 0° to 70° C 28-pin Plastic SOIC
CS8414-CS 0° to 70° C 28-pin Plastic SOIC
I
CS8413
VD+ DGND VA+ FILT AGND
78
22 20 21
MCK
19
9
RXP
RXN 10
RS422
Receiver
Clock and Data Recovery
De-MUX
CS8414
IEnable and Status
25
ERF
14
INT
VD+ DGND VA+ FILT AGND
78
22 20 21
MCK
19
9
RXP
RXN 10
RS422
Receiver
Clock and Data Recovery
De-MUX
MUX
13
CS12/
FCK
16
SEL
MUX
6 5 4 3 2 27
C0/ Ca/ Cb/ Cc/ Cd/ Ce/
E0 E1 E2 F0 F1 F2
Audio
Serial Port
26 SDATA
12 SCK
11 FSYNC
Configurable
Buffer
Memory
13 A4/FCK
4
A3-A0
8
D7-D0
24
23
CS
RD/WR
M3 M2 M1 M0
17 18 24 23
Audio
Serial Port
Registers
25 15
ERF CBL
26 SDATA
12 SCK
11 FSYNC
1
14
28
C
U
VERF
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Copyright © Cirrus Logic, Inc. 1998
(All Rights Reserved)
OCT ‘98
DS240F1
1
1 page  
CS8413 CS8414
SWITCHING CHARACTERISTICS - SERIAL PORTS
(TA = 25 °C; VD+, VA+ = 5V ± 5%; Inputs: Logic 0 = DGND, Logic 1 = VD+; CL = 20 pF)
Parameters
Symbol Min Typ Max
SCK Frequency
Master Mode (Notes 6 and 7)
Slave Mode
(Note 7)
SCK falling to FSYNC delay Master Mode (Notes 7 and 8)
SCK Pulse Width Low
Slave Mode (Note 7)
SCK Pulse Width High
Slave Mode (Note 7)
SCK rising to FSYNC edge delay Slave Mode (Notes 7 and 8)
FSYNC edge to SCK rising setup Slave Mode (Notes 7 and 8)
SCK falling (rising) to SDATA valid
(Note 8)
C, U, CBL valid to FSYNC edge CS8414
(Note 8)
MCK to FSYNC edge delay
FSYNC from RXN/RXP
fsck
tsfdm
tsckl
tsckh
tsfds
tfss
tssv
tcuvf
tmfd
- OWRx32 -
OWRx32 - 128 x FS
-20 -
20
40 -
-
40 -
-
20 -
-
20 -
-
- - 20
- 1/fsck -
- 15 -
Units
Hz
Hz
ns
ns
ns
ns
ns
ns
s
ns
Notes: 6. The output word rate, OWR, refers to the frequency at which an audio sample is output from the part.
(A stereo pair is two audio samples.) Therefore, in Master mode, there are always 32 SCK periods in
one audio sample. In Slave mode, exactly 32 SCK periods per audio sample must be provided in most
serial port formats. Therefor, if SCK is 128 x Fs, then SCK must be gated to provide exactly 32 periods
per audio sample.
7. In Master mode, SCK and FSYNC are outputs. In Slave mode, they are inputs. In the CS8413, control
reg. 2 bit 1, MSTR, selects master. In the CS8414, formats 1, 3 and 9 are slaves.
8. The table above assumes data is output on the falling edge and latched on the rising edge. With the
CS8413 the edge is selectable. The table is defined for the CS8413 with control reg. 2 bit 0, SCED, set
to one, and for the CS8414 in formats 2, 3, 5, 6 and 7. For the other formats, the table and figure edges
must be reversed (i.e. “rising” to “falling” and vice versa.)
FSYNC
tsfds
SCK
SDATA
tfss tsckl tsckh
tssv
MSB
(Mode 1)
FSYNC
tsfds
tfss tsckl tsckh
SCK
SDATA
tssv
MSB
(Mode 3)
Serial Output Timing - Slave Mode
MCK
FSYNC
tmfd
FSYNC Generated From
Received Data
C, U
FSYNC
tsfdm
SCK
(Modes 2,3,5,6, tssv
7,10,12, and 13)
SCK
(Modes 0,1,4,
8,9, and 11)
SDATA
tcuvf
DS240F1
Serial Output Timing -
Master Mode & C, U Port
5
5 Page 
CS8413 CS8414
status register 1 to generate an interrupt pulse. A
“0” masks that particular status bit from causing an
interrupt.
Status register 2 (SR2) reports all the conditions
that can affect the error flag bit in SR1 and the error
pin (ERF), and can specify the received clock fre-
quency. As previously mentioned, the first five bits
of SR2 are AND’ed with their interrupt enable bits
(in IER2) and then OR’ed to create ERF. The V,
PARITY, CODE and LOCK bits are latches which
are set when their corresponding conditions occur,
and are reset when SR2 is read. The ERF pin is as-
serted each time the error occurs assuming the in-
terrupt enable bit in IER2 is set for that particular
error. When the ERF pin is asserted, the ERF bit in
SR1 is set. If the ERF bit was not set prior to the
ERF pin assertion, an interrupt will be generated
(assuming bit 3 in IER1 is set). Although the ERF
pin is asserted for each occurrence of an enabled er-
ror condition, the ERF bit will only cause an inter-
rupt once if SR1 is not read.
X:01 7 6 5
4
32
10
SR2. FREQ2 FREQ1 FREQ0 Reserved LOCK CODE PARITY V
IER2. TEST1 TEST0
INT. ENABLE BITS
FOR ABOVE
SR2:
FREQ2:
FREQ1:
FREQ0:
LOCK:
CODE:
PARITY:
V:
The 3 FREQ bits indicate incoming sample frequency.
(must have 6.144 MHz clock on FCK pin and FCEN
must be “1”)
Out-of-Lock error
Coding violation
Parity error
Validity bit high
IER2: TEST1,0: (0 on power-up) Must stay at “0”.
INT. ENABLES: Enables the corresponding bit in SR2.
A “1” enables the interrupt. A “0” masks the interrupt.
Figure 7. Status/IEnable Register 2
V is the validity status bit which is set any time the
received validity bit is high. PARITY is set when a
parity error is detected. CODE is set when a bi-
phase coding error is detected. LOCK is asserted
when the receiver PLL is not locked and occurs
when there is no input on RXP/RXN, or if the re-
ceived frequency is out of the receiver lock range
(28.4 kHz to 100 kHz).
The upper three bits in SR2, FREQ2-FREQ0, can
report the receiver frequency when the receiver is
locked. These bits are only valid when FCEN in
control register 1 is set, and a 6.144 MHz clock is
applied to the FCK pin. When FCEN is set, the
A4/FCK pin is used as FCK and A4 is internally set
to zero; therefore, only the lower half of the buffer
can be accessed. Table 1 lists the frequency ranges
reported. The FREQ bits are updated three times
per block and the clock on the FCK pin must be val-
id for two thirds of a block for the FREQ bits to be
accurate. The FREQ bits are invalid when the PLL
is out of lock.
FREQ2 FREQ1 FREQ0
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
Sample Frequency
Out of Range
reserved
reserved
96 kHz ± 4%
88.2 kHz ± 4%
48 kHz ± 4%
44.1 kHz ± 4%
32 kHz ± 4%
Table 1. Incoming Sample Frequency Bits
IEnable register 2 has corresponding interrupt en-
able bits for the first five bits in SR2. A “1” enables
the condition in SR2 to cause ERF to go high, while
a “0” masks that condition. Bit 5 is unused and bits
6 and 7, the two most significant bits, are factory
test bits and must be set to zero when writing to this
register. The CS8413 sets these bits to zero on pow-
er-up.
Control Registers
The CS8413 contains two control registers. Control
register 1 (CR1), at address 2, selects system level
features, while control register 2 (CR2), at address
3, configures the audio serial port.
In control register 1, when RST is low, all outputs
are reset except MCK (FSYNC and SCLK are high
impedance). The CS8413 should be reset imediate-
ly after power-up and any time the user performs a
DS240F1
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS8413-CS.PDF ] | |
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