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PDF CS8129YTHA5 Data sheet ( Hoja de datos )
| Número de pieza | CS8129YTHA5 | |
| Descripción | 5V/ 750mA Low Dropout Linear Regulator with Lower RESET Threshold | |
| Fabricantes | Cherry Semiconductor Corporation | |
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CS8129
5V, 750mA Low Dropout Linear
Regulator with Lower RESET Threshold
Description
The CS8129 is a precision 5V linear reg-
ulator capable of sourcing 750mA.
The RESET threshold voltage has been
lowered to 4.2V so that the regulator
can be used with 4V microprocessors.
The lower RESET threshold also per-
mits operation under low battery condi-
tions (5.5V plus a diode). The RESET Õs
delay time is externally programmed
using a discrete RC network. During
power up, or when the output goes out
of regulation, RESET remains in the
low state for the duration of the delay.
This function is independent of the
input voltage and will function correct-
ly as long as the output voltage remains
at or above 1V. Hysteresis is included in
the Delay and the RESET comparators
to improve noise immunity. A latching
discharge circuit is used to discharge
the delay capacitor when it is triggered
by a brief fault condition.
The regulator is protected against a
variety of fault conditions: i.e. reverse
battery, overvoltage, short circuit and
thermal runaway conditions. The regu-
lator is protected against voltage tran-
sients ranging from -50V to +40V. Short
circuit current is limited to 1.2A (typ).
The CS8129 is packaged in a 5 lead
TOÐ220 and a 16 lead surface mount
package.
Block Diagram
Features
s 5V +/- 3% Regulated
Output
s Low Dropout Voltage
(0.6V @ 0.5A)
s 750mA Output Current
Capability
s Reduced RESET Threshold
for use with 4V Micro-
processors
s Externally Programmed
RESET Delay
s Fault Protection
Reverse Battery
60V, -50V Peak Transient
Voltage
Short Circuit
Thermal Shutdown
Over Voltage
Shutdown
Delay
Pre- Regulated Supply
Regulator for Circuit Bias
Bandgap
Reference
Charge
Current
Generator
Thermal
Shutdown
Latching Discharge
QS
R
-
+
Error
Amplifier
Anti-Saturation
and
Current Limit
VIN
VOUT
VOUTSENSE
Package Options
16 Lead SOIC Wide
VIN 1
NC
NC
Gnd
Gnd
RESET
NC
Delay
VOUT
NC
VOUT(SENSE)
Gnd
Gnd
Gnd
NC
NC
5 Lead TO-220
Gnd
VDISCHARGE
Rev. 3/31/99
+ Delay Comparator
-
RESET
1
1 VIN
2 RESET
3 Gnd
4 Delay
5 VOUT
1
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
A ¨ Company
1 page  
VOUT
VRT(ON)
VRT(OFF)
VRH
RESET Circuit Waveform
RESET
(3)
VRL
Delay
VDC(HI)
VDC(LO)
VDH
(1)
(2)
tDelay
(2)
(1) = No Delay Capacitor
(2) = With Delay Capacitor
(3) = Max: RESET Voltage (1.0V)
VDIS
RESET Circuit Functional Description
The CS8129 RESET function has hysteresis on both the
reset and delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1V.
The RESET circuit output is an open collector type with
ON and OFF parameters as specified. The RESET output
NPN transistor is controlled by the two circuits described
(see Block Diagram).
Low Voltage Inhibit Circuit
This circuit monitors output voltage, and when output
voltage is below the specified minimum causes the
RESET output transistor to be in the ON (saturation)
state. When the output voltage is above the specified level,
this circuit permits the RESET output transistor to go into
the OFF state if allowed by the RESET Delay circuit.
Reset Delay Circuit
This circuit provides a programmable (by external capaci-
tor) delay on the RESET output lead. The Delay lead pro-
vides source current to the external delay capacitor only
when the "Low Voltage Inhibit" circuit indicates that out-
put voltage is above VRT(ON). Otherwise, the Delay lead
sinks current to ground (used to discharge the delay
capacitor). The discharge current is latched ON when the
output voltage is below VRT(OFF). The Delay capacitor is
fully discharged anytime the output voltage falls out of
regulation, even for a short period of time. This feature
ensures a controlled RESET pulse is generated following
detection of an error condition. The circuit allows
the RESET output transistor to go to the OFF (open) state
only when the voltage on the Delay lead is higher than
VDC(HI).
The Delay time for the RESET function is calculated from
the formula:
Delay time = CDelay x VDelay Threshold
ICharge
Delay time = CDelay(µF) x 3.2 x 10 5
If CDelay=0.1µF, Delay time (ms)=32ms ± 50%: i.e. 16ms to
48ms. The tolerance of the capacitor must be taken into
account to calculate the total variation in the delay time.
5
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CS8129YTHA5.PDF ] | |
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