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PDF CS5211ED14 Data sheet ( Hoja de datos )
| Número de pieza | CS5211ED14 | |
| Descripción | Low Voltage Synchronous Buck Controller | |
| Fabricantes | ON Semiconductor | |
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CS5211
Low Voltage Synchronous
Buck Controller
The CS5211 is a low voltage synchronous buck controller. It
contains all required circuitry for a synchronous buck converter using
external N–Channel MOSFETs. High current internal gate drivers are
capable of driving high gate capacitance of low RDS(on) NFETs for
better efficiency. The V2™ control architecture is used to achieve
unmatched transient response, the best overall regulation and the
simplest loop compensation. The CS5211 is in a 14–pin package to
allow the designer added flexibility.
The CS5211 provides overcurrent protection, undervoltage lockout,
Soft Start and built in adaptive nonoverlap. The CS5211 also provides
adjustable fixed frequency range of 150 kHz to 750 kHz. This gives
the designer more flexibility to make efficiency and component size
compromises. The CS5211 will operate over a 4.5 V to 14 V range
using either single of dual input voltage.
Features
• Switching Regulator Controller
– N–Channel Synchronous Buck Design
– V2 Control Topology
– 200 ns Transient Response
– Programmable Fixed Frequency of 150 kHz–750 kHz
– 1.0 V 1.5% Internal Reference
– Lossless Inductor Sensing Overcurrent Protection
– Hiccup Mode Short Circuit Protection
– Programmable Soft Start
– 40 ns GATE Rise and Fall Times (3.3 nF Load)
– 70 ns Adaptive FET Nonoverlap Time
– Differential Remote Sense Capability
• System Power Management
– 5.0 V or 12 V Operation
– Undervoltage Lockout
– On/Off Control Through Use of the COMP Pin
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MARKING
DIAGRAM
14
SOIC–14
D SUFFIX
CASE 751A
CS5211x
AWLYWW
1
x
A
WL, L
YY, Y
WW, W
= E or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
1
GATE(H)
BST
LGND
VFFB
VFB
COMP
SGND
PGND
GATE(L)
VC
IS+
IS–
VCC
ROSC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
© Semiconductor Components Industries, LLC, 2001
December, 2001 – Rev. 4
1
Publication Order Number:
CS5211/D
1 page  
CS5211
PACKAGE PIN DESCRIPTION
PIN NO.
PIN SYMBOL
1 GATE(H)
2 BST
3 LGND
4 VFFB
5 VFB
6 COMP
7 SGND
8 ROSC
9 VCC
10 IS–
11 IS+
12 VC
13 GATE(L)
14 PGND
FUNCTION
High Side Switch FET driver pin. Capable of delivering peak currents of 1.0 A.
Power supply input for the high side driver.
Reference ground. All control circuits are referenced to this pin. IC substrate connection.
Input for the PWM comparator.
Error amplifier input.
Error Amp output. PWM Comparator reference input. A capacitor to LGND provides error amp
compensation.
Internal reference is connected to this ground. Connect directly at the load for ground remote
sensing.
A resistor from this pin to SGND sets switching frequency.
Input Power Supply Pin. It supplies power to control circuitry. A 0.1 µF Decoupling cap is rec-
ommended.
Negative input for overcurrent comparator.
Positive input for overcurrent comparator.
Power supply input for the low side driver.
Low Side Synchronous FET driver pin. Capable of delivering peak currents of 1.0 A.
High Current ground for the GATE(H) and GATE(L) pins.
VFFB
0.5 V
Σ
PWM Comparator
Reset Dominant
RQ
COMP
VFB
SGND
VCC
IS+
IS–
LGND
− Error Amp
+
1.0 V
ART Ramp
OSC
ROSC
Fault
SQ
PWM FF
0.8 V
VSTART
100 % DC
− Comparator
+
UVLO
Comparator
UVLO
Set Dominant
Fault
SQ
60 mV
OC
Comparator
0.25 V
−
+
RQ
5.0 µA
COMP Discharge COMP
Figure 2. Block Diagram
BST
GATE(H)
VC
GATE(L)
PGND
ROSC
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5
5 Page 
CS5211
Feedback Divider Selection
The feedback voltage measured at VFB during normal
regulation will be 1.0 V. This voltage is compared to an
internal 1.0 V reference and is used to regulate the output
voltage. The bias current into the error amplifier is 1.0 µA
max, so select the resistor values so that this current does not
add an excessive offset voltage.
VFFB Feedback Selection
To take full advantage of the V2 control scheme, a small
amount of output ripple must be fed back to the VFFB pin,
typically 50 mV. For most application, this requirement is
simple to achieve and the VFFB can be connected directly to
the VFB pin. There are some application that have to meet
stringent load transient requirements. One of the key factor
in achieving tight dynamic voltage regulation is low ESR.
Low ESR at the regulator output results in low output
voltage ripple. This situation could result in increase noise
sensitivity and a potential for loop instability. In applications
where the output ripple is not sufficient, the performance of
the CS5211 can be improved by adding a fixed amount
external ramp compensation to the VFFB pin. Refer to Figure
7, the amount of ramp at the VFFB pin depends on the switch
node Voltage, Feedback Voltage, R1 and C2.
Vramp + (Vsw * VFB) tonń(R1 C2)
where:
Vramp = amount of ramp needed;
Vsw = switch note voltage;
VFB = voltage feedback, 1 V;
ton = switch on–time.
To minimize the lost in efficiency R1 resistance should be
large, typically 100 k or larger. With R1 chosen, C2 can be
determined by the following;
C2 + (Vsw * VFB) tonń(R1 Vramp)
C1 is used as a bypass capacitor and its value should be
equal to or greater than C2.
Vsw
R1
C1
VFFB
C2
R2
1.0 k
VFB
Figure 7. Small RC Filter Providing the Proper Voltage
Ramp at the Beginning of Each On–Time Cycle
Maximum Frequency Operation
The minimum pulse width may limit the maximum
operating frequency. The duty factor, given by the
output/input voltage ratio, multiplied by the period
determines the pulse width during normal operation. This
pulse width must be greater than 200 ns, or duty cycle jitter
could become excessive. For low pulse widths below 300 ns,
external slope compensation should be added to the VFFB
pin to increase the PWM ramp signal and improve stability.
50 mV of added ramp at the VFFB pin is typically enough.
Current Sense Component Selection
The current limit threshold is set by sensing a 60 mV
voltage differential between the IS+ and IS– pins. Referring
to Figure 8, the time constant of the R2,C1 filter should be
set larger than the L/R1 time constant under worst case
tolerances, to prevent overshoot in the sensed voltage and
tripping the current limit too low. Resistor R3 of value equal
to R2 is added for bias current cancellation. R2 and R3
should not be made too large, to reduce errors from bias
current offsets. For typical L/R time constants, a 0.1 µF
capacitor for C1 will allow R2 to be between 1.0 k and 10 kΩ.
The current limit without R4 and R5, which are optional,
is given by 60 mV/R1, where R1 is the internal resistance of
the inductor, obtained from the manufacturer. The addition
of R5 can be used to decrease the current limit to a value
given by:
ILIM + (60 mV * (VOUT R3ń(R3 ) R5))ńR1
where VOUT is the output voltage.
Similiarly, omitting R5 and adding R4 will increase the
current limit to a value given by:
ILIM + 60 mVńR1 (1 ) R2ńR4)
Essentially, R4 or R5 are used to increase or decrease the
inductor voltage drop which corresponds to 60 mV at the IS+
and IS– pins.
IS–
60 mV Trip
R3
R5
IS+
R2
C1
Switching
Node
R4
L1
L
R1
Figure 8. Current Limit
VOUT
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