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A42L2604S-45 PDF даташит

Спецификация A42L2604S-45 изготовлена ​​​​«AMIC Technology» и имеет функцию, называемую «4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE».

Детали детали

Номер произв A42L2604S-45
Описание 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Производители AMIC Technology
логотип AMIC Technology логотип 

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A42L2604S-45 Даташит, Описание, Даташиты
A42L2604 Series
Preliminary
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Document Title
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Revision History
Rev. No.
0.0
0.1
0.2
0.3
History
Initial issue
Modify symbol HE dimensions in TSOP 24L package information
Add -45 grade and modify the AC, DC data
Add -U type spec.
Modify DC data and all parts guarantee self-refresh mode
Issue Date
June 13, 2001
July 10, 2001
November 30, 2001
June 10, 2002
Remark
Preliminary
PRELIMINARY (June, 2002, Version 0.3)
AMIC Technology, Inc.









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A42L2604S-45 Даташит, Описание, Даташиты
A42L2604 Series
Preliminary
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Features
n Organization: 4,194,304 words X 4 bits
n Part Identification
- A42L2604 (2K Ref.)
n Single 3.3V power supply/built-in VBB generator
n Low power consumption
- Operating: 80mA (-45 max)
- Standby: 1.0mA (TTL), 1.5mA (CMOS),
350µA (Self-refresh current)
n High speed
- 45/50 ns RAS access time
- 20/22 ns column address access time
- 12/13 ns CAS access time
- 18/20 ns EDO Page Mode Cycle Time
General Description
The A42L2604 is a new generation randomly accessed
memory for graphics, organized in a 4,194,304-word by
4-bit configuration. This product can execute Write and
Read operation via CAS pin.
The A42L2604 offers an accelerated Fast Page Mode
Pin Configuration
n SOJ
n TSOP
VCC
I/O 0
I/O 1
WE
RAS
NC
1
2
3
4
5
6
A10
A0
A1
A2
A3
VCC
8
9
10
11
12
13
26 VSS
25 I/O3
24 I/O2
23 CAS
22 OE
21 A9
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
VCC
I/O 0
I/O 1
WE
RAS
NC
1
2
3
4
5
6
A10
A0
A1
A2
A3
VCC
8
9
10
11
12
13
26 VSS
25 I/O3
24 I/O2
23 CAS
22 OE
21 A9
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
n Industrial operating temperature range: -40°C to +85°C
for -U
n Fast Page Mode with Extended Data Out
n 2K Refresh Cycle in 32ms
n Read-modify-write, RAS -only, CAS -before- RAS ,
Hidden refresh capability
n TTL-compatible, three-state I/O
n JEDEC standard packages
- 300mil, 24/26-pin SOJ
- 300mil, 24/26-pin TSOP type II package
cycle with a feature called Extended Data Out (EDO).
This allow random access of up to 2048(2K Ref.) words
within a row at a 56/50 MHz EDO cycle, making the
A42L2604 ideally suited for graphics, digital signal
processing and high performance computing systems.
Pin Descriptions
Symbol
A0 – A10
I/O0 - I/O3
RAS
CAS
WE
OE
VCC
VSS
NC
Description
Address Inputs (2K product)
Data Input/Output
Row Address Strobe
Column Address Strobe
Write Enable
Output Enable
3.3V Power Supply
Ground
No Connection
PRELIMINARY (June, 2002, Version 0.3)
1
AMIC Technology, Inc.









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A42L2604S-45 Даташит, Описание, Даташиты
Selection Guide
Symbol
tRAC
tAA
tCAC
tOEA
tRC
tPC
Description
Maximum RAS Access Time
Maximum Column Address Access Time
Maximum CAS Access Time
Maximum Output Enable ( OE ) Access Time
Minimum Read or Write Cycle Time
Minimum EDO Cycle Time
Functional Description
The A42L2604 reads and writes data by multiplexing an
22-bit address into a 11-bit(2K) row and column address.
RAS and CAS are used to strobe the row address and the
column address, respectively.
A Read cycle is performed by holding the WE signal high
during RAS / CAS operation. A Write cycle is executed by
holding the WE signal low during RAS / CAS operation;
the input data is latched by the falling edge of WE or
CAS , whichever occurs later. The data inputs and outputs
are routed through 4 common I/O pins, with RAS , CAS ,
WE and OE controlling the in direction.
EDO Page Mode operation all 2048(2K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
CAS . While holding RAS low, CAS can be toggled to
strobe changing column addresses, thus achieving shorter
cycle times.
The A42L2604 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which
keeps the output drivers on during the CAS precharge
time (tcp). Since data can be output after CAS goes high,
the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain
A42L2604 Series
-45 -50 Unit
45 50 ns
20 22 ns
12 13 ns
12 13 ns
76 84 ns
18 20 ns
valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.
A memory cycle is terminated by returning both RAS and
CAS high. Memory cell data will retain its correct state by
maintaining power and accessing all 2048(2K)
combinations of the 11-bit(2K) row addresses, regardless
of sequence, at least once every 32ms through any RAS
cycle (Read, Write) or RAS Refresh cycle ( RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh counter
and controller.
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and CAS .
It is recommended that RAS and CAS track with VCC or
be held at a valid VIH during Power-On to avoid current
surges.
PRELIMINARY (June, 2002, Version 0.3)
2
AMIC Technology, Inc.










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