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A420616V-50 PDF даташит

Спецификация A420616V-50 изготовлена ​​​​«AMIC Technology» и имеет функцию, называемую «1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE».

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Номер произв A420616V-50
Описание 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Производители AMIC Technology
логотип AMIC Technology логотип 

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A420616V-50 Даташит, Описание, Даташиты
A420616 Series
Preliminary
1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Document Title
1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Revision History
Rev. No.
0.0
0.1
0.2
History
Initial issue
Modify AC, DC data
Modify DC data and all parts guarantee self-refresh mode
Issue Date
June 23, 1999
February 7, 2002
June 10, 2002
Remark
Preliminary
PRELIMINARY (June, 2002, Version 0.2)
AMIC Technology, Inc.









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A420616V-50 Даташит, Описание, Даташиты
A420616 Series
Preliminary
1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Features
n Organization: 1,048,576 words X 16 bits
n Part Identification
- A420616 (1K Ref.)
n Single 5.0V power supply/built-in VBB generator
n Low power consumption
- Operating: 120mA (-45 max)
- Standby: 1.0mA (TTL), 1.0mA (CMOS)
1.5mA (Self-refresh current)
n High speed
- 45/50 ns RAS access time
- 20/22 ns column address access time
- 12/13 ns CAS access time
- 18/20 ns EDO Page Mode Cycle Time
General Description
The A420616 is a new generation randomly accessed
memory for graphics, organized in a 1,048,576-word by
16-bit configuration. This product can execute Byte Write
and Byte Read operation via two CAS pins.
The A420616 offers an accelerated Fast Page Mode
Pin Configuration
nSOJ
n TSOP
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 VSS
41 I/O15
40 I/O14
39 I/O13
38 I/O12
37 VSS
36 I/O11
35 I/O10
34 I/O9
33 I/O8
32 NC
31 LCAS
30 UCAS
29 OE
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 VSS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 VSS
43 I/O15
42 I/O14
41 I/O13
40 I/O12
39 VSS
38 I/O11
37 I/O10
36 I/O9
35 I/O8
34 NC
33 NC
32 LCAS
31 UCAS
30 OE
29 A9
28 A8
27 A7
26 A6
25 A5
24 A4
23 VSS
n Industrial operating temperature range: -40°C to 85°C
for -U
n Fast Page Mode with Extended Data Out
n Separate CAS ( UCAS , LCAS ) for byte selection
n 1K Refresh Cycle in 16ms
n Read-modify-write, RAS -only, CAS -before- RAS ,
Hidden refresh capability
n TTL-compatible, three-state I/O
n JEDEC standard packages
- 400mil, 42-pin SOJ
- 400mil, 44/50 TSOP type II package
This allow random access of up to 1024 words within a
row at a 56/50 MHz EDO cycle, making the A420616
ideally suited for graphics, digital signal processing and
high performance computing systems.
Pin Descriptions
Symbol
A0 – A9
I/O0 - I/O15
RAS
LCAS
UCAS
WE
OE
VCC
VSS
NC
Description
Address Inputs
Data Input/Output
Row Address Strobe
Column Address Strobe for Lower Byte
(I/O0 – I/O7)
Column Address Strobe for Upper Byte
(I/O8 – I/O15)
Write Enable
Output Enable
5.0V Power Supply
Ground
No Connection
cycle with a feature called Extended Data Out (EDO).
PRELIMINARY (June, 2002, Version 0.2)
1
AMIC Technology, Inc.









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A420616V-50 Даташит, Описание, Даташиты
A420616 Series
Selection Guide
Symbol
tRAC
tAA
tCAC
tOEA
tRC
tPC
Description
Maximum RAS Access Time
Maximum Column Address Access Time
Maximum CAS Access Time
Maximum Output Enable ( OE ) Access Time
Minimum Read or Write Cycle Time
Minimum EDO Cycle Time
-45 -50 Unit
45 50 ns
20 22 ns
12 13 ns
12 13 ns
76 84 ns
18 20 ns
Functional Description
The A420616 reads and writes data by multiplexing an 20-
bit address into a 10-bit row and 10-bit column address.
RAS and CAS are used to strobe the row address and the
column address, respectively.
The A420616 has two CAS inputs: LCAS controls I/O0-
I/O7, and UCAS controls I/O8 - I/O15, UCAS and LCAS
function in an identical manner to CAS in that either will
generate an internal CAS signal. The CAS function and
timing are determined by the first CAS ( UCAS or
LCAS ) to transition low and by the last to transition high.
Byte Read and Byte Write are controlled by using LCAS
and UCAS separately.
A Read cycle is performed by holding the WE signal high
during RAS / CAS operation. A Write cycle is executed by
holding the WE signal low during RAS / CAS operation;
the input data is latched by the falling edge of WE or
CAS , whichever occurs later. The data inputs and outputs
are routed through 16 common I/O pins, with RAS , CAS ,
WE and OE controlling the in direction.
EDO Page Mode operation all 1024(1K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
CAS . While holding RAS low, CAS can be toggled to
strobe changing column addresses, thus achieving shorter
cycle times.
The A420616 offers an accelerated Fast Page Mode cycle
through a feature called Extended Data Out, which keeps
the output drivers on during the CAS precharge time (tcp).
Since data can be output after CAS goes high, the user is
not required to wait for valid data to appear before starting
the next access cycle. Data-out will remain valid as long as
RAS and OE are low, and WE is high; this is the only
characteristic which differentiates Extended Data Out
operation from a standard Read or Fast Page Read.
A memory cycle is terminated by returning both RAS and
CAS high. Memory cell data will retain its correct state by
maintaining power and accessing all 1024(1K)
combinations of the 10-bit row addresses, regardless of
sequence, at least once every 16ms through any RAS
cycle (Read, Write) or RAS Refresh cycle ( RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh counter
and controller.
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and CAS .
It is recommended that RAS and CAS track with VCC or
be held at a valid VIH during Power-On to avoid current
surges.
PRELIMINARY (June, 2002, Version 0.2)
2
AMIC Technology, Inc.










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