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PDF AD1858 Data sheet ( Hoja de datos )
| Número de pieza | AD1858 | |
| Descripción | Stereo/ Single Supply 16-/ 18- and 20-Bit Sigma-Delta DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Stereo, Single Supply
16-, 18- and 20-Bit Sigma-Delta DACs
AD1857/AD1858
FEATURES
Low Cost, High Performance Stereo DACs
128 Times Oversampling Interpolation Filter
Multibit ⌺⌬ Modulator with Triangular PDF Dither
Discrete Time and Continuous Time Analog
Reconstruction Filters
Extremely Low Out-of-Band Energy
Buffered Outputs with 2 k⍀ Output Load Drive
94 dB Dynamic Range, –90 dB THD+N Performance
Digital De-emphasis and Mute
؎0.1؇C Maximum Phase Linearity Deviation
Continuously Variable Sample Rate Support
Power-Down Mode
16-, 18- and 20-Bit I2S-Justified, Left-Justified Modes
Offered on AD1857
Accepts 24-Bit Word
16-Bit Right-Justified and DSP Serial Port Modes
Offered on AD1858
Single +5 V Supply
20-Pin SSOP Package
APPLICATIONS
Digital Cable TV and Direct Broadcast Satellite Set-Top
Decoder Boxes
Video Laser Disk, Video CD and CD-I Players
High Definition Televisions, Digital Audio Broadcast
Receivers
CD, CD-R, DAT, DCC and MD Players
Digital Audio Workstations, Computer Multimedia
Products
PRODUCT OVERVIEW
The AD1857/AD1858 are complete single-chip stereo digital
audio playback components. They each comprise an advanced
digital interpolation filter, a revolutionary “linearity-compensated”
multibit sigma-delta (∑∆) modulator with dither, a jitter-tolerant
DAC, switched capacitor and continuous time analog filters and
analog output drive circuitry. Other features include digital
de-emphasis processing and mute. The AD1857/AD1858
support continuously variable sample rates with essentially
linear phase response, and support 50/15 µs digital de-emphasis
intended for “Redbook” 44.1 kHz sample frequency playback
from Compact Discs. The user must provide a master clock that
is synchronous with the left/right clock at 256 or 384 times the
intended sample frequency.
The AD1857/AD1858 have a simple but very flexible serial data
input port that allows for glueless interconnection to a variety of
ADCs, DSP chips, AES/EBU receivers and sample rate con-
verters. The AD1857 serial data input port can be configured
in either 16-bit, 18-bit or 20-bit left-justified or I2S-justified
modes. The AD1858 serial data input port can be configured in
either 16-bit right-justified or DSP serial port compatible modes.
The AD1857/AD1858 accept serial audio data in MSB first,
twos-complement format. A power-down mode is offered to
minimize power consumption when the device is inactive. The
AD1857/AD1858 operate from a single +5 V power supply.
They are fabricated on a single monolithic integrated circuit and
housed in 20-pin SSOP packages for operation over the
temperature range 0°C to +70°C.
DIGITAL
SUPPLY
2
FUNCTIONAL BLOCK DIAGRAM
COMMON
MODE
CLOCK CLOCK
MODE
IN
16-/18-/20-BIT
DIGITAL 3
DATA INPUT
SERIAL DATA
INTERFACE
AD1857/AD1858
VOLTAGE
REFERENCE
CLOCK
CIRCUIT
SERIAL
MODE
128x
INTERPOLATION
FILTER
128x
INTERPOLATION
FILTER
MUTE
MUTE
MULTIBIT
Σ∆ MODULATOR
MULTIBIT
Σ∆ MODULATOR
DAC
DAC
ANALOG
FILTER
ANALOG
FILTER
OUTPUT
BUFFER
OUTPUT
BUFFER
ANALOG
OUTPUTS
DE-EMPHASIS
MUTE
POWER-DOWN/RESET
4
ANALOG
SUPPLY
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
1 page  
AD1857/AD1858
PIN LIST
Digital Audio Serial Input Interfaces
Pin Name
Number
I/O
SDATA
20
I
BCLK
19
I
LRCLK
MODE
18
3
I
I
Description
Serial input, MSB first, containing two channels of 16, 18 or 20 bits (AD1857) or
16 bits (AD1858) of twos complement data per channel.
Bit clock input for input data. Need not run continuously; may be gated or used in a
burst fashion.
Left/right clock input for input data. Must run continuously.
Input serial data port mode control. Selects between I2S-justified (HI) and left-justified
(LO) on the AD1857. Selects between DSP serial port style mode (HI) and right-
justified (LO) on the AD1858. The state of the mode pin should be changed only when
the AD1857/AD1858 is held in reset (PD/RST LO). Otherwise, the AD1857/
AD1858 serial port may lose synchronism.
Control and Clock Signals
Pin Name
Number
I/O Description
PD/RST
DEEMP
MUTE
MCLK
384/256
2
5
15
1
6
I Power-Down/Reset. The AD1857/AD1858 are placed in a low power consumption
“sleep” mode when this pin is held LO. The AD1857/AD1858 are reset on the
rising edge of this signal. Connect HI for normal operation.
I De-emphasis. Digital de-emphasis is enabled when this input signal is HI. This is
used to impose a 50/15 µs response characteristic on the output audio spectrum at
an assumed 44.1 kHz sample rate.
I Mute. Assert HI to mute both stereo analog outputs of the AD1857/AD1858.
Deassert LO for normal operation.
I Master Clock Input. Connect to an external clock source at either 256 or 384 times
the intended sample frequency as determined by the 384/256 pin. Must be synchro-
nous with LRCLK, but may have any phase with respect to LRCLK.
I Selects the master clock mode as either 384 times the intended sample frequency
(HI) or 256 times the intended sample frequency (LO). The state of this input
should be hardwired to logic LO or logic HI or may be changed while the AD1857/
AD1858 is in power-down/reset. It must not be changed while the AD1857/AD1858
is operational.
Analog Signals
Pin Name
Number
I/O
Description
FILT
CMOUT
11
10
OUTL
OUTR
8
13
O Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage
reference with parallel 10 µF and 0.1 µF capacitors to the AGND pin.
O Voltage Reference Common Mode Output. Should be decoupled with 10 µF
capacitor to the AGND pin or plane. This output is available externally for dc
coupling and level-shifting. CMOUT should not have any signal dependent load,
or used where it will sink or source current.
O Left channel line level analog output.
O Right channel line level analog output.
Power Supply Connections and Miscellaneous
Pin Name
Number
I/O Description
AVDD
AGND
DVDD
DGND
N/C
7, 14
9, 12
17
16
4
I Analog Power Supply. Connect to analog +5 V supply.
I Analog Ground.
I Digital Power Supply. Connect to digital +5 V supply.
I Digital Ground.
No Connect. Reserved. Do not connect.
REV. 0
–5–
5 Page 
AD1857/AD1858
LRCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LEFT CHANNEL
RIGHT CHANNEL
MSB MSB-1
LSB+2 LSB+1 LSB
MSB MSB-1
LSB+2 LSB+1 LSB
Figure 12. AD1858 Left-Justified DSP Serial Port Style
MSB MSB-1
LRCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LEFT CHANNEL
LSB MSB MSB-1 MSB-2
RIGHT CHANNEL
LSB+2 LSB+1 LSB MSB MSB-1 MSB-2
LSB+2 LSB+1 LSB MSB MSB-1
Figure 13. AD1857/AD1858 32 ؋ FS Packed Mode
Figure 12 shows the AD1858 left-justified DSP serial port style
mode. LRCLK must pulse HI for at least one bit clock period
before the MSB of the left channel is valid, and LRCLK must
pulse HI again for at least one bit clock period before the MSB
of the right channel is valid. Data is valid on the falling edge of
BCLK. Note that in this mode, it is the responsibility of the DSP
to ensure that the left data is transmitted with the first LRCLK
pulse, the right data is transmitted with the second LRCLK pulse,
and synchronism is maintained from that point forward.
Note that in 16-bit input mode, the AD1857/AD1858 are
capable of a 32 × FS BCLK frequency “packed mode” where
the MSB is left-justified to an LRCLK transition, and the LSB
is right-justified to an LRCLK transition. LRCLK is HI for the
left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. Packed mode can be used when the
AD1857 is programmed in left-justified mode, or when the
AD1858 is programmed in right-justified mode. Packed mode
is shown in Figure 13.
Master Clock
The synchronous master clock of the AD1857/AD1858 is
supplied by an external clock source applied to MCLK. Figure
14 shows example connections. Do not change the state of the
384/256 pin while the AD1857/AD1858 is operational; this pin
should be hardwired LO or HI. Alternatively, its state may be
changed while the PD/RST pin is asserted LO.
MCLK FREQUENCY
12.288MHz
11.2896MHz
8.192MHz
18.432MHz
16.9344MHz
12.288MHz
256 MODE 384 MODE
384/256 = LO 384/256 = HI
SAMPLE RATE
48kHz
44.1kHz
32kHz
1
MCLK
6
384/256
Figure 14. AD1857/AD1858 Clock Connections
Digital Mute
The AD1857/AD1858 offer a control pin that mutes the analog
output. By asserting the MUTE (Pin 15) signal HI, both the
left channel and the right channel are muted. The AD1857/
AD1858 have been designed to minimize pops and clicks when
muting and unmuting the device. The AD1857/AD1858
include a zero crossing detector which attempts to implement
mute on waveform zero crossings only. If a zero crossing is not
found within 1024 input sample periods (approximately 23
milliseconds at 44.1 kHz), the output is muted regardless.
Output Drive, Buffering and Loading
The AD1857/AD1858 analog output stage is able to drive a 2 kΩ
load. If lower impedance loads must be driven, an external
buffer stage such as the Analog Devices SSM2142 should be
used. The analog output is generally ac coupled with a 10 µF
capacitor as shown in Figure 21. It is possible to dc couple the
AD1857/AD1858 output into an op amp stage using the
CMOUT signal as a bias point.
On-Chip Voltage Reference
The AD1857/AD1858 include an on-chip voltage reference that
establishes the output voltage range. The nominal value of this
reference is +2.25 V, which corresponds to a line output voltage
swing of 3 V p-p. The line output signal is centered around a
voltage established by the CMOUT (common-mode output)
(Pin 10). The reference must be bypassed both on the FILT
input (Pin 11) with 10 µF and 0.1 µF capacitors, and on the
CMOUT output (Pin 10) with 10 µF and 0.1 µF capacitors, as
shown in Figure 21. Both the FILT pin and the CMOUT pin
use the AGND ground. The on-chip voltage reference may be
overdriven with an external reference source by applying this
voltage to the FILT pin. CMOUT and FILT must still be
bypassed as shown in Figure 21. An external reference can be
useful to calibrate multiple AD1857/AD1858 DACs to the same
gain. Reference bypass capacitors larger than those suggested
can be used to improve the signal-to-noise performance of the
AD1857/AD1858.
Power-Down and Reset
The PD/RST input (Pin 2) is used to control the power consumed
by the AD1857/AD1858. When PD/RST is held LO, the
AD1857/AD1858 are placed in a low dissipation power-down
state. When PD/RST is brought HI, the AD1857/AD1858
become ready for normal operation. The master clock (MCLK,
Pin 1) must be running for a successful reset or power-down
operation to occur. The PD/RST signal must be LO for a
minimum of four master clock periods (326 ns with a 12.288 MHz
MCLK frequency).
When the PD/RST input (Pin 2) is brought HI, the AD1857/
AD1858 are reset. All registers in the AD1857/AD1858 digital
engine (serial data port, interpolation filter and modulator) are
zeroed, and the amplifiers in the analog section are shorted
during the reset operation. The AD1857/AD1858 have been
designed to minimize pops and clicks when entering and exiting
the power-down state.
REV. 0
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD1858.PDF ] | |
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