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PDF AD5582 Data sheet ( Hoja de datos )
| Número de pieza | AD5582 | |
| Descripción | QUAD/ Parallel-Input/ Voltage Output/ 12-/10-Bit Digital-to-Analog Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD5582 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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PRELIMINARY TECHNICAL DATA
a
QUAD, Parallel-Input, Voltage Output,
12-/10-Bit Digital-to-Analog Converter
AD5582/AD5583
FEATURES
12-Bit Linearity and Monotonic –40oC to +125oC
Single +5V to +12V or dual ±5V supply
Unipolar or Bipolar Operation
Double Buffered Registers Enable Simultaneous Multi-
Channels Update
4 Separate Rail-to Rail Reference Inputs
Parallel Interface
Data Readback Capability
5µs Settling Time
APPLICATIONS
Process Control Equipment
Closed Loop Servo Control
Data Acquisition Systems
Digitally Controlled Calibration
Motor Control
Optical Network Control Loops
GENERAL DESCRIPTION
The AD5582/AD5583 family of quad, 12-/10-bit, voltage-output
digital-to-analog converter is designed to operate from a single +5
to +15 volt or a dual ±5V supply. Built using a CBCMOS process,
this monolithic DAC offers the user low cost, and ease-of-use in
single or dual-supply systems.
The applied external reference VREF determines the full-scale
output voltage. Valid VREF values include VSS<VREF<VDD resulting
in a wide selection of full scale outputs. For multiplying
applications AC inputs can be as large as |VDD-VSS|. Two on-board
precision trimmed resistors are available for 4-Quadrant
configurations.
A doubled-buffered parallel interface offers 25Mbps data load rates.
A common level-sensitive load-DAC strobe (LDAC) input allows
simultaneous update of all DAC outputs from previously loaded
Input Registers. An external asynchronous reset (RS) forces all
registers to the zero code state when MSB='0' or to midscale when
MSB='1'.
Both parts are offered in the same pin-out to allow users to select
the amount of resolution appropriate for their application without
circuit card redesign.
The AD5582/AD5583 are specified over the extended industrial
(-40°C to +125°C) temperature range. Packages available include
thin 1.1 mm TSSOP-48 package.
FUNCTIONAL DIAGRAM
A1 37
A0 36
ADDR
DECODE
DB11 24
DB10 25
DB9 26
DB8 27
DB7 28
DB6 29
DB5 30
DB4 31
DB3 32
I
N
T
E
R
F
A
C
E
Do
Di
IN
REG
DB2 33
DB1 34
DB0 35
OE
CS 23
W/R 22
VLOGIC 19
CONTROL
L OGIC
MSB 17
RS 18
LDAC 21
16 20
DVDD
DGND
VRLA VRHA VRLB VRHBVDD
12
34 5
DAC
REG
6 VOA
7 VOB
20kΩ
20kΩ
AD5582
38 RA
39 RB
40 RC
8 AGND
9 VOC
10 VOD
15 14
13 12 11
VRHDVRLD VRHCVRLCVSS
+2.5V
ADR421
RA
RB RC
-2.5V
V REFH
A
B
C
D
AD5582
DAC A
V REFL
A
B
C
D
DAC B
DAC C
DAC D
±2.5V
±2.5V
±2.5V
±2.5V
DIG ITAL CIRCUITRY O MITTED FO R CLARITY
Figure 1 Using Onboard Offset resistors to generate a negative
voltage REF
REV PrC, 23 APR '01
Information furnished by Analog Devices is believed to be accurate and reliable. However,
no responsibility is assumed by Analog Devices for its use; nor for any infringements of
patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax:781/326-8703
©Analog Devices, Inc., 2000
1 page  
PRELIMINARY TECHNICAL DATA
AD5582/AD5583
PIN CONFIGURATION
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
NOTE: Pin Out not finalized!
Please contact Analog Devices Inc. for final version
Pin# Name
. VRLA
VRHA
VRLB
VRHB
VDD
VOA
VOB
RA
RB
RC
AGND
VOC
VOD
VSS
VRLC
VRHC
VRLD
VRHD
DGND
DVDD
LDAC
RS
MSB
VL
W/R
CS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
A0
A1
Description
Voltage Reference Low Input Terminal DAC A
Voltage Reference High Input Terminal DAC A
Voltage Reference Low Input Terminal DAC B
Voltage Reference High Input Terminal DAC B
Positive Power Supply
DAC A Output
DAC B output
End Tap Offset Resistor
Center Tap Offset Resistor
End Tap Offset Resistor
Analog Ground
Voltage Out DAC C
DAC D Output
Negative Power Supply
Voltage Reference Low Input Terminal DAC C
Voltage Reference High Input Terminal DAC C
Voltage Reference Low Input Terminal DAC D
Voltage Reference High Input Terminal DAC D
Digital Ground
DAC Register Load, active low level sensitive
Reset strobe
Reset Mode: MSB=0 Code = 000H, MSB=1 Code
800H
Logic Supply Voltage
Write Read Mode select
Chip Select, active low
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 8
Data Bit 9
Data Bit 10
Data Bit 11
Address Input 0
Address Input 1
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future
manufacture unless otherwise agreed to in writing.
REV PrC, 23 APR '01
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AD5582.PDF ] | |
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