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PDF AD5531 Data sheet ( Hoja de datos )
| Número de pieza | AD5531 | |
| Descripción | Serial Input/ Voltage Output 12-/14-Bit DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Pin-Compatible 12- and 14-Bit DACs
Serial Input, Voltage Output
Maximum Output Voltage Range of ؎10 V
Data Readback
3-Wire Serial Interface
Clear Function to a User-Defined Voltage
Power-Down Function
Serial Data Output for Daisy-Chaining
16-Lead TSSOP Packages
APPLICATIONS
Industrial Automation
Automatic Test Equipment
Process Control
General-Purpose Instrumentation
Serial Input, Voltage Output
12-/14-Bit DACs
AD5530/AD5531
GENERAL DESCRIPTION
The AD5530 and AD5531 are single 12-/14-bit serial input,
voltage output DACs, respectively.
They utilize a versatile 3-wire interface that is compatible with
SPI™, QSPI™, MICROWIRE™, and DSP interface standards.
Data is presented to the part in the format of a 16-bit serial word.
Serial data is available on the SDO pin for daisy-chaining pur-
poses. Data readback allows the user to read the contents of the
DAC register via the SDO pin.
The DAC output is buffered by a gain of 2 amplifier and refer-
enced to the potential at DUTGND. LDAC may be used to update
the output of the DAC asynchronously. A power-down (PD) pin
allows the DAC to be put into a low power state, and a CLR pin
allows the output to be cleared to a user-defined voltage, the
potential at DUTGND.
The AD5530 and AD5531 are available in 16-lead TSSOP
packages.
REFIN
REFAGND
LDAC
RBEN
SDIN
FUNCTIONAL BLOCK DIAGRAM
VSS VDD
R –R
+
12-/14-BIT DAC
AD5530/AD5531
+
– VOUT
R
DAC REGISTER
SHIFT REGISTER
POWER-DOWN
CONTROL LOGIC
R
DUTGND
CLR
PD
GND
SCLK SYNC
SDO
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
1 page  
AD5530/AD5531
DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS1, 2, 3 (VDD = 10.8 V to 16.5 V, VSS = –10.8 V
to –16.5 V; VSS = –15 V ±10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Description
fMAX
t1
t2
t3
t4
t5
t6
t7
t8
t12
t13
t14
t15
t16
t17
2
500
200
200
50
40
50
40
15
50
130
50
50
50
100
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
SCLK Frequency
SCLK Cycle Time
SCLK Low Time
SCLK High Time
SYNC to SCLK Falling Edge Setup Time
SCLK Falling Edge to SYNC Rising Edge
Min SYNC High Time
Data Setup Time
Data Hold Time
CLR Pulsewidth
SCLK Falling Edge to SDO Valid
SCLK Falling Edge to SDO Invalid
RBEN to SCLK Falling Edge Setup Time
RBEN Hold Time
RBEN Falling Edge to SDO Valid
1Guaranteed by design. Not production tested.
2Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns
(10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3SDO; RPULLUP = 5 kΩ, CL = 15 pF.
Specifications subject to change without notice.
SCLK
SYNC
SDIN
SDO
(DAISY
CHAINING)
RBEN
SDO
(READBACK)
t1 t3
t4 t5 t2
t6
MSB
DB15
DB14
t7 t8
DB11
LSB
DB0
t13 MSB
DB15
t14
DB11
LSB
DB0
t15
t16
t17 t13
MSB
0
0
Figure 2. Timing Diagram for Daisy-Chaining and READBACK Mode
RB13
t14
RB0
LSB
REV. 0
–5–
5 Page 
AD5530/AD5531
+15V
2
6
8
VOUT
REFIN
VOUT
AD586
5
R1
10k⍀
AD5530/
AD5531*
C1
1F 4
DUTGND
VOUT
(–10V TO +10V)
SIGNAL
GND
REFAGND GND
VSS
–15V
SIGNAL
GND
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 5. Bipolar ±10 V Operation
2 REFIN
0V
–2 REFIN
DAC INPUT CODE 000 001
(3)FFF
ADSP-2101/
ADSP-2103*
FO
TFS
DT
SCLK
AD5530/
AD5531*
LDAC
SYNC
SDIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 7. AD5530/AD5531 to ADSP-21xx Interface
AD5530/AD5531 to 8051 Interface
A serial interface between the AD5530/AD5531 and the 8051 is
shown in Figure 8. TXD of the 8051 drives SCLK of the AD5530/
AD5531, while RXD drives the serial data line, SDIN. P3.3 and
P3.4 are bit-programmable pins on the serial port and are used
to drive SYNC and LDAC respectively.
The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user will have to ensure that the data in the
SBUF register is arranged correctly as the DAC expects MSB first.
80C51/80L51*
P3.4
P3.3
RXD
TXD
AD5530/
AD5531*
LDAC
SYNC
SDIN
SCLK
Figure 6. Output Voltage vs. DAC Input Codes (Hex)
*ADDITIONAL PINS OMITTED FOR CLARITY
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5530/AD5531 is via a serial
bus that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
(minimum) interface consisting of a clock signal, a data signal,
and a synchronization signal. The AD5530/AD5531 requires a
16-bit data word with data valid on the falling edge of SCLK.
For all the interfaces, the DAC output update may be done
automatically when all the data is clocked in or asynchronously
under the control of LDAC.
The contents of the DAC register may be read using the readback
function. RBEN is used to frame the readback data, which is
clocked out on SDO. The following figures illustrate these DACs
interfacing with a simple 4-wire interface. The serial interface of
the AD5530/AD5531 may be operated from a minimum of
three wires.
Figure 8. AD5530/AD5531 to 8051 Interface
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RXD is clocked out of the microcontroller on the rising
edge of TXD and is valid on the falling edge. As a result no glue
logic is required between this DAC and microcontroller interface.
The 8051 transmits data in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. As the DAC expects a
16-bit word, P3.3 must be left low after the first 8 bits are transferred.
After the second byte has been transferred, the P3.3 line is taken
high. The DAC may be updated using LDAC via P3.4 of the 8051.
AD5530/AD5531 to MC68HC11 Interface
Figure 9 shows an example of a serial interface between the
AD5530/AD5531 and the MC68HC11 microcontroller. SCK
of the 68HC11 drives the SCLK of the DAC, while the MOSI
output drives the serial data lines, SDIN. SYNC is driven from
one of the port lines, in this case PC7.
AD5530/AD5531 to ADSP-21xx
An interface between the AD5530/AD5531 and the ADSP-21xx
is shown in Figure 7. In the interface example shown, SPORT0
is used to transfer data to the DAC. The SPORT control regis-
ter should be configured as follows: internal clock operation,
alternate framing mode; active low framing signal.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
output is updated using the LDAC pin via the DSP. Alternatively,
the LDAC input could be tied permanently low and then the
update takes place automatically when TFS is taken high.
MC68HC11*
PC6
PC7
MOSI
SCK
AD5530/
AD5531*
LDAC
SYNC
SDIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. AD5530/AD5531 to MC68HC11 Interface
REV. 0
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD5531.PDF ] | |
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