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даташит AD53020 PDF ( Datasheet )

AD53020 Datasheet Download - Analog Devices

Номер произв AD53020
Описание Four Channel ECL Delay Line
Производители Analog Devices
логотип Analog Devices логотип 



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AD53020 Даташит, Описание, Даташиты
a
FEATURES
Four Delay Lines with the Ability to Independently
Adjust All Edges
Pin Compatible and Functionally Equivalent with the
BT624
Reduced Power Dissipation
44-Lead PLCC Package with Internal Heat Spreader
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Clocked ECL Circuits
PRODUCT DESCRIPTION
The AD53020 is a four-channel delay line designed for use in
automatic test equipment and digital logic systems. High speed
bipolar transistors and a 44-lead plastic PLCC package with
internal heat spreader provide high frequency performance at a
minimum of space, cost and power dissipation.
Featuring full pin compatibility and functional equivalence to
the BT624, the AD53020 offers independent analog control of
positive and negative edges with five delay ranges. The AD53020
offers attractive performance with optimized power dissipation
and linear delay vs. program voltage control. This device is also
very stable over operating conditions and has very low jitter.
Digital inputs are ECL compatible. They can either be pro-
vided independently for each channel (IN1, IN1 through IN4,
IN4), or fanned out to all channels from Channel 2 (IN2,
IN2). The choice of these two options is made by setting the
DRVMODE input, with ECL Logic 0 providing four indepen-
dent channels, and ECL Logic 1 enabling a logical OR function
between each channel and the Channel Number 2.
For maximum timing accuracy, differential signals are recom-
mended for use with the digital inputs. However, single-ended
operation is also supported and it is facilitated through the use
of the VBB midpoint level generated on-chip. To make use of
this feature, connect the VBB output to the inverting input of
each channel. It is also advisable, when using the VBB output,
to decouple this signal with a 0.1 µF ceramic capacitor to ground.
The outputs of the AD53020 are ECL compatible and should
be terminated by 50 to –2.0 V at the inputs of the gates
they drive.
Four Channel ECL Delay Line
AD53020
FUNCTIONAL BLOCK DIAGRAM
GND
S0 S1
IN1, IN1
AD53020
IN2, IN2
DRVMODE
IN3, IN3
IN4, IN4
VEE
VWIDTH1
OUT1
OUT1
VDELAY1
VWIDTH2
OUT2
OUT2
VDELAY2
VWIDTH3
OUT3
OUT3
VDELAY3
VWIDTH4
OUT4
OUT4
VDELAY4
VBB COMP1 COMP2 REXT1 REXT2
The delay is programmed through the VDELAY and VWIDTH
pins for each channel. The acceptable range is –1.3 V to –0.1 V,
representing the longest and the shortest delays provided by the
device. An 0.01 µF ceramic capacitor to ground is recom-
mended for each input. The bias current for each input is fixed
by an internal current mirror. The value of the bias current is
set by the external resistor at REXT1. A 1.3 kresistor to
ground at this pin establishes 1 mA bias in each input. The
nominal voltage at the REXT1 pin is –1.3 V.
The VDELAY affects both the positive and negative edges in all
modes. The VWIDTH is an additional delay adjustment that is
active in Modes 2, 3 and 5. VWIDTH has no effect in Modes 0
and 1. For Modes 2 and 3, the effect of the VWIDTH adjust-
ment is to increase or decrease the delay of the negative edge
relative to the positive edge. In Mode 5, the total delay for both
positive and negative edges is set by the combination of VDELAY
and VWIDTH.
(continued on page 4)
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999







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AD53020 Даташит, Описание, Даташиты
AD53020–SPECIFICATIONS AD53020-Test Conditions (Unless otherwise noted): Recommended Operating
Conditions with all OUT and OUT outputs terminated through 50 to –2.0 V, REXT1 = 1.3 k, REXT2 = 2.94 k. Typical values are based on
nominal temperature, TA = +25؇C, and nominal supply voltage, VEE = –5.2 V.
DC CHARACTERISTICS1
Parameter
Symbol T(؇C)
Min
Typ
Max Units
DIGITAL INPUT HIGH VOLTAGE
IN, IN, DRVMODE, S0, S1
VIH 70
–1.070
0.000
V
DIGITAL INPUT LOW VOLTAGE
IN, IN, DRVMODE, S0
DIGITAL INPUT LOW VOLTAGE, S1
VIL 70
VIL 70
–1.950
VEE
–1.450
–1.450
V
V
S1 THIRD STATE (EXTENDED DELAY)
Full VEE
–3.2 V
DIGITAL OUTPUT HIGH VOLTAGE
DIGITAL OUTPUT LOW VOLTAGE
DIGITAL INPUT BIAS CURRENT
IN, IN, DRVMODE, S0, S1
POWER SUPPLY REJECTION RATIO2
VOH
VOL
IIN
PSRR
70
70
Full
–1.000
–1.950
–100 to
+100
0.5
–0.735
–1.600
V
V
µA
% Tpd/V
VEE SUPPLY CURRENT
Mode 0
Modes 1, 2
Modes 3, 5
IEE Full
IEE Full
IEE Full
174 200 mA
225 250 mA
267 290 mA
NOTES
1The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least two
minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board.
2This parameter is fully characterized, but not production tested.
Specifications subject to change without notice.
AC CHARACTERISTICS1
Parameter
Symbol
Min
Typ
Max Units
MINIMUM PROPAGATION DELAYS2
Mode S1 S0 VDELAY
0 0 0 –0.1 V
1 0 1 –0.1 V
2 1 0 –0.1 V
3 1 1 –0.1 V
5 VEE 1 –0.1 V
DELAY ADJUSTMENT RANGES
Mode S1 S0
0 00
1 01
2 10
3 11
5 VEE 1
MINIMUM PULSEWIDTH3
Tpd Min
3.6
4.5
5.4 ns
Tpd Min
4.9
6.3
7.3 ns
Tpd Min
3.9
5.3
6.8 ns
Tpd Min
5.2
7.1
8.8 ns
Tpd Min
6.8
8.8
10.3 ns
Tpd Span
14.0
19.0
24.7 ns
Tpd Span
22.9
31.4
37.8 ns
Tpd Span
13.2
18.9
24.6 ns
Tpd Span
22.0
31.5
40.6 ns
Tpd Span
29.3
44.5
52.0 ns
1.9 ns
RISING EDGE DELAY VS. VWIDTH DELAY
Change (Modes 2 and 3)3
30 ps
DELAY VS. DUTY CYCLE3, 4
50 ps
VWIDTH RANGE OF ADJUSTMENT
(VDELAY = –0.6 V, MODES 2 AND 3, DELAY
RELATIVE TO VWIDTH = –0.7 V)
VWIDTH = –0.1 V
VWIDTH = –1.1 V
VWIDTH = –1.3 V
–5.5 –4.0 ns
+5.5 ns
+4.0 +6.5
ns
–2– REV. A







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AD53020 Даташит, Описание, Даташиты
AD53020
Parameter
Symbol
Min
Typ
Max Units
RISING TO FALLING EDGE DELAY MATCHING
(VDELAY = VFALL = –0.5 V)3
Modes 0, 1, 5
Modes 2, 3
0.1 ns
1.0 ns
PROPAGATION DELAY TEMPERATURE
COEFFICIENT3, 5
0.05 % Tpd/°C
OUTPUT RISE/FALL TIMES
(20% to 80%)3
DELAY LINEARITY3
550
MONOTONIC
ps
NOTES
1The specified limits shown can be met only after thermal equilibrium has been established. Thermal equilibrium is established by applying power for at least two
minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board.
2All minimum propagation delay time measurements refer to both rising and falling edges for Modes 0, 1, 5; these measurements refer to rising edges for Modes 2 and
3 only. DRVMODE is logically low.
3This parameter is fully characterized, but not production tested.
4Delay on leading and trailing edges are measured by setting VDELAY = VWIDTH = –0.7 V. The variations for each delay are measured by changing the input duty
cycle from 5% to 95% at a constant frequency of 10 MHz.
5Propagation delay temperature coefficient measured at VDELAY = VWIDTH = –0.7 V.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
Parameter
Symbol Min Max Units
VEE (Relative to GND)
Voltage on Any Digital Pin
Output Current
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature2
(Soldering, 5 sec)
TA
TS
TJ
TSOL
–6.0 0
V
VEE
50
V
mA
–55 +70 °C
–65 +150 °C
+150 °C
+260 °C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Absolute maximum limits apply individually,
not in combination. Exposure to absolute maximum rating conditions for ex-
tended periods of time may affect device reliability.
2To ensure lead solderability, handling with bare hands should be avoided and the
device should be stored in environments at 24°C ± 5°C (75°F ± 10°F) with relative
humidity not to exceed 65%.
Model
AD53020
ORDERING GUIDE
Package
Description
Package
Option
44-Lead Plastic Leaded Chip Carrier P-44A
(PLCC)
PIN CONFIGURATION
6 5 4 3 2 1 44 43 42 41 40
IN4 7
VEE4 8
VDELAY4 9
VWIDTH4 10
VDELAY3 11
VWIDTH3 12
VDELAY2 13
VWIDTH2 14
VDELAY1 15
VWIDTH1 16
VBB 17
PIN 1
IDENTIFIER
AD53020
TOP VIEW
(Not to Scale)
39 IN1
38 IN1
37 GND1
36 COMP1
35 REXT1
34 COMP2
33 REXT2
32 DRVMODE
31 S0
30 S1
29 GND1
18 19 20 21 22 23 24 25 26 27 28
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53020 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–










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