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PDF AD53020 Data sheet ( Hoja de datos )
| Número de pieza | AD53020 | |
| Descripción | Four Channel ECL Delay Line | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD53020 (archivo pdf) en la parte inferior de esta página. Total 4 Páginas | ||
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FEATURES
Four Delay Lines with the Ability to Independently
Adjust All Edges
Pin Compatible and Functionally Equivalent with the
BT624
Reduced Power Dissipation
44-Lead PLCC Package with Internal Heat Spreader
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Clocked ECL Circuits
PRODUCT DESCRIPTION
The AD53020 is a four-channel delay line designed for use in
automatic test equipment and digital logic systems. High speed
bipolar transistors and a 44-lead plastic PLCC package with
internal heat spreader provide high frequency performance at a
minimum of space, cost and power dissipation.
Featuring full pin compatibility and functional equivalence to
the BT624, the AD53020 offers independent analog control of
positive and negative edges with five delay ranges. The AD53020
offers attractive performance with optimized power dissipation
and linear delay vs. program voltage control. This device is also
very stable over operating conditions and has very low jitter.
Digital inputs are ECL compatible. They can either be pro-
vided independently for each channel (IN1, IN1 through IN4,
IN4), or fanned out to all channels from Channel 2 (IN2,
IN2). The choice of these two options is made by setting the
DRVMODE input, with ECL Logic 0 providing four indepen-
dent channels, and ECL Logic 1 enabling a logical OR function
between each channel and the Channel Number 2.
For maximum timing accuracy, differential signals are recom-
mended for use with the digital inputs. However, single-ended
operation is also supported and it is facilitated through the use
of the VBB midpoint level generated on-chip. To make use of
this feature, connect the VBB output to the inverting input of
each channel. It is also advisable, when using the VBB output,
to decouple this signal with a 0.1 µF ceramic capacitor to ground.
The outputs of the AD53020 are ECL compatible and should
be terminated by 50 Ω to –2.0 V at the inputs of the gates
they drive.
Four Channel ECL Delay Line
AD53020
FUNCTIONAL BLOCK DIAGRAM
GND
S0 S1
IN1, IN1
AD53020
IN2, IN2
DRVMODE
IN3, IN3
IN4, IN4
VEE
VWIDTH1
OUT1
OUT1
VDELAY1
VWIDTH2
OUT2
OUT2
VDELAY2
VWIDTH3
OUT3
OUT3
VDELAY3
VWIDTH4
OUT4
OUT4
VDELAY4
VBB COMP1 COMP2 REXT1 REXT2
The delay is programmed through the VDELAY and VWIDTH
pins for each channel. The acceptable range is –1.3 V to –0.1 V,
representing the longest and the shortest delays provided by the
device. An 0.01 µF ceramic capacitor to ground is recom-
mended for each input. The bias current for each input is fixed
by an internal current mirror. The value of the bias current is
set by the external resistor at REXT1. A 1.3 kΩ resistor to
ground at this pin establishes 1 mA bias in each input. The
nominal voltage at the REXT1 pin is –1.3 V.
The VDELAY affects both the positive and negative edges in all
modes. The VWIDTH is an additional delay adjustment that is
active in Modes 2, 3 and 5. VWIDTH has no effect in Modes 0
and 1. For Modes 2 and 3, the effect of the VWIDTH adjust-
ment is to increase or decrease the delay of the negative edge
relative to the positive edge. In Mode 5, the total delay for both
positive and negative edges is set by the combination of VDELAY
and VWIDTH.
(continued on page 4)
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet AD53020.PDF ] | |
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