AD7484 Datasheet PDF - Analog Devices
| Part Number | AD7484 | |
| Description | 3MSPS/ 14-Bit SAR ADC | |
| Manufacturers | Analog Devices | |
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PRELIMINARY TECHNICAL DATA
=
3MSPS,
14-Bit SAR ADC
Preliminary Technical Data
AD7484
FEATURES
Fast Throughput Rate: 3Msps
Wide Input Bandwidth: 50MHz
No Pipeline Delays with SAR ADC
Excellent DC Accuracy Performance
Two Parallel Interface Modes
Low Power:
90mW (Full-Power) and 5mW (NAP Mode)
Standby Mode: 1µA max
Single +5V Supply Operation
Internal +2.5V Reference
Full-Scale Overrange Mode (using 15th bit)
System Offset Removal via User Access Offset Register
Nominal 0 to +2.5V Input with Shifted Range Capability
Pin Compatible Upgrade of 12-Bit AD7482
GENERAL DESCRIPTION
The AD7484 is a 14-bit, high speed, low power, succes-
sive-approximation ADC. The part features a parallel
interface with throughput rates up to 3Msps. The part
contains a low-noise, wide bandwidth track/hold amplifier
which can handle input frequencies in excess of 50MHz.
The conversion process is a proprietary algorithmic suc-
cessive-approximation technique which results in no
pipeline delays. The input signal is sampled and a conver-
sion is initiated on the falling edge of the CONVST
signal. The conversion process is controlled via an inter-
nally trimmed oscillator. Interfacing is via standard
parallel signal lines making the part directly compatible
with microcontrollers and DSPs.
The AD7484 provides excellent ac and dc performance
specifications. Factory trimming ensures high dc accuracy
resulting in very low INL, offset and gain errors.
The part uses advanced design techniques to achieve very
low power dissipation at high throughput rates. Power
consumption in normal mode of operation is 90mW.
There are two power-saving modes: a NAP mode, which
keeps the reference circuitry alive for a quick power up
while consuming 5mW and a STANDBY mode which
reduces power consumption to a mere 5µW.
FUNCTIONAL BLOCK DIAGRAM
VREF3
AVDD AGND CBIAS DVDD DGND
BUF
2.5V
REFERENCE
VREF1
VREF2
VIN T/H
14-Bit Error
Correcting SAR
AD7484
MODE1
MODE2
CLIP
NAP
STBY
RESET
CONVST
VDRIVE
CONTROL
LOGIC AND I/O
REGISTERS
D14
D13
D12
D11
D10
D9
D8
D7
The AD7484 features an on-board +2.5V reference but
the part can also accomodate an externally-provided
+2.5V reference source. The nominal analog input range
is 0 to +2.5V but an offset shift capability allows this
nominal range to be offset by +/-200mV. This allows the
user considerable flexibility in setting the bottom end
reference point of the signal range, a useful feature when
using single-supply op-amps.
The AD7484 also provides the user with an 8% overrange
capability via a 15th bit. Thus, if the analog input range
strays outside the nominal by up to 8%, the user can still
accurately resolve the signal by using the 15th bit.
The AD7484 is powered from a +4.75V to +5.25V sup-
ply. The part also provides a VDRIVE pin which allows the
user to set the voltage levels for the digital interface lines.
The range for this VDRIVE pin is from +2.7V to +5.25V.
The part is housed in a 48-pin LQFP package and is
specified over a -40°C to +85°C temperature range.
REV. PrC 7/13/01
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
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Pin
Mnemonic
AVDD
CBIAS
AGND
VIN
VREF1
VREF2
VREF3
STBY
NAP
DVDD
DGND
VDRIVE
CONVST
RESET
MODE2
MODE1
CLIP
CS
RD
WRITE
BUSY
D0 - D13
D14
PRELIMINARY TECHNICAL DATA
PIN FUNCTION DESCRIPTION
AD7484
Description
Positive power supply for analog circuitry.
Decoupling pin for internal bias voltage. A 100nF capacitor should be placed between this pin and
AGND.
Power supply ground for analog circuitry.
Analog input. Single-ended analog input channel.
Reference Output. VREF1 connects to the output of the internal 2.5V reference. A 1µF capacitor must
be placed between this pin and AGND.
Reference Input. A 1µF capacitor must be placed between this pin and AGND. When using an external
voltage reference source, the reference voltage should be applied to this pin.
Reference decoupling pin. When using the internal reference, a 100nF must be connected from this pin
to AGND. When using an external reference source, this pin should be connected directly to AGND.
Standby logic input. When this pin is logic high, the device will be placed in Standby mode. See Power
Saving Section for further details.
Nap logic input. When this pin is logic high, the device will be placed in a very low power mode. See
Power Saving Section for further details.
Positive power supply for digital circuitry.
Ground reference for digital circuitry.
Logic Power Supply Input. The voltage supplied at this pin will determine at what voltage
the interface logic of the AD7484 will operate.
Convert Start Logic Input. A conversion is initiated on the falling edge of CONVST signal. The input
track/hold amplifier goes from track mode to hold mode and the conversion process commences.
Reset Logic Input. A logic 0 on this pin resets the internal state machine and terminates a conversion
that may be in progress. Holding this pin low keeps the part in a reset state.
Operating Mode Logic Input. See Table 3 for details.
Operating Mode Logic Input. See Table 3 for details.
Logic input. A logic high on this pin enables output clipping. In this mode, any input voltage that is
greater than positive full scale or less than negative full scale will be clipped to all 1’s or all 0’s
respectively. Further details are given in the Offset / Overrange setion.
Chip Select Logic Input. This pin is used in conjunction with RD to access the conversion result. The
data bus is brought out of tri-state and the current contents of the output register driven onto the data
lines following the falling edge of both CS and RD. CS is also used in conjunction with WRITE to
perform a write to the Offset Register. CS can be hardwired permanently low.
Read Logic Input. Used in conjunction with CS to access the conversion result.
Write Logic Input. Used in conjunction with CS to write data to the Offset Register. When the desired
offset word has been placed on the data bus, the WRITE line should be pulsed high. It is the falling
edge of this pulse which latches in the word into the Offset Register.
Busy Logic Output. This pin indicates the status of the conversion process. The BUSY signal goes low
after the falling edge of CONVST and stays low for the duration of the conversion. In Parallel Mode 2,
the BUSY signal returns high when the conversion result has been clocked into the output register. In
Parallel Mode 1, the BUSY signal returns high as soon as the conversion has been completed but the
conversion result does not get clocked into the output register until the falling edge of the next
CONVST pulse.
Data I/O Bits (D13 is MSB). These are tri-state pins that are controlled by CS, RD and WRITE.
The operating voltage level for these pins is determined by the VDRIVE input.
Data Output Bit for overranging. If the over range feature is not used, this pin should be pulled to
DGND via a 100k⍀ resistor.
REV. PrC 7/13/01
–5–
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| Information | Total 12 Pages | |
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| Download | [ AD7484.PDF Datasheet ] | |
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