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AD9712B PDF даташит

Спецификация AD9712B изготовлена ​​​​«Analog Devices» и имеет функцию, называемую «12-Bit/ 100 MSPS D/A Converters».

Детали детали

Номер произв AD9712B
Описание 12-Bit/ 100 MSPS D/A Converters
Производители Analog Devices
логотип Analog Devices логотип 

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AD9712B Даташит, Описание, Даташиты
a
12-Bit, 100 MSPS
D/A Converters
FEATURES
100 MSPS Update Rate
ECL/TTL Compatibility
SFDR @ 1 MHz: 70 dBc
Low Glitch Impulse: 28 pV-s
Fast Settling: 27 ns
Low Power: 725 mW
1/2 LSB DNL (B Grade)
40 MHz Multiplying Bandwidth
APPLICATIONS
ATE
Signal Reconstruction
Arbitrary Waveform Generators
Digital Synthesizers
Signal Generators
GENERAL DESCRIPTION
The AD9712B and AD9713B D/A converters are replacements
for the AD9712 and AD9713 units which offer improved ac and
dc performance. Like their predecessors, they are 12-bit, high
speed digital-to-analog converters fabricated in an advanced
oxide isolated bipolar process. The AD9712B is an ECL-
compatible device featuring update rates of 100 MSPS mini-
mum; the TTL-compatible AD9713B will update at 80 MSPS
minimum.
AD9712B/AD9713B
FUNCTIONAL BLOCK DIAGRAM
LATCH 26
ENABLE
28
DIGITAL
INPUTS
D1
THRU
D12
1
AD9712B/AD9713B
(MSB)
DECODERS
AND
DRIVERS
SWITCH
NETWORK
11 (LSB)
R SET 24
INTERNAL
VOLTAGE
REFERENCE
+
CONTROL
AMP
20
REFERENCE
OUT
19
CONTROL
AMP IN
14 I OUT
16 I OUT
17 REFERENCE
IN
18 CONTROL
AMP OUT
Designed for direct digital synthesis, waveform reconstruction,
and high resolution imaging applications, both devices feature
low glitch impulse of 28 pV-s and fast settling times of 27 ns.
Both units are characterized for dynamic performance and have
excellent harmonic suppression.
The AD9712B and AD9713B are available in 28-pin plastic
DIPs and PLCCs, with an operating temperature range of
–25°C to +85°C. Both are also available for extended tempera-
ture ranges of –55°C to +125°C in cerdips and 28-pin LCC
packages.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703









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AD9712B Даташит, Описание, Даташиты
AD9712B/AD9713B–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS [–VS = –5.2 V; +VS = +5 V (AD9713B only); Reference Voltage = –1.2 V;
RSET = 7.5 k; VOUT = 0 V (virtual ground); unless otherwise noted]
Parameter (Conditions)
Temp
Test
Level
AD9712B/AD9713B
AN/AP
Min Typ Max
AD9712B/AD9713B AD9712B/AD9713B AD9712B/AD9713B
BN/BP
SE/SQ
TE/TQ
Min Typ Max Min Typ Max Min Typ Max Units
RESOLUTION
12
12 12
12 Bits
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
(“Best Fit” Straight Line)
+25°C
Full
+25°C
Full
I
VI
I
VI
–1.25
–2.0
–1.5
–2.0
1.0
1.0
+1.25 –0.75 0.5 +0.75 –1.5 1.0 +1.5
2.0 –1.5
1.5 –2.0
2.0
1.5 –1.0 0.75 1.0 –1.75 1.5 1.75
2.0 –1.75
1.75 –2.0
2.0
–1.0 0.5
–1.5
–1.25 1.0
–1.75
+1.0 LSB
1.5 LSB
1.25 LSB
1.75 LSB
Parameter (Conditions)
INITIAL OFFSET ERROR
Zero-Scale Offset Error
Full-Scale Gain Error1
Offset Drift Coefficient
REFERENCE/CONTROL AMP
Internal Reference Voltage
Internal Reference Voltage Drift
Internal Reference Output Current
Amplifier Input Impedance
Amplifier Bandwidth
REFERENCE INPUT2
Reference Input Impedance
Reference Multiplying Bandwidth3
DYNAMIC PERFORMANCE
Full-Scale Output Current4
Output Compliance Range
Output Resistance
Output Capacitance
Output Update Rate5
Output Settling Time (tST)6
Output Propagation Delay (tPD)7
Glitch Impulse8
Output Rise Time9
Output Fall Time9
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (tS)10
Input Hold Time (tH)11
Latch Pulse Width (tLPW) (LOW)
(Transparent)
AC LINEARITY12
Spurious-Free Dynamic Range (SFDR)
1.23 MHz; 10 MSPS; 2 MHz Span
5.055 MHz; 20 MSPS; 2 MHz Span
10.1 MHz; 50 MSPS; 2 MHz Span
16 MHz; 40 MSPS; 10 MHz Span
Temp
+25°C
Full
+25°C
Full
+25°C
+25°C
Full
Full
Full
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
Full
Full
Full
Full
+25°C
+25°C
Full
+25°C
Full
+25°C
Full
+25°C
+25°C
+25°C
+25°C
AD9712B
Test All Grades
Level Min
Typ
Max
I 0.5 2.5
VI 5.0
I 1.0 5
VI 8
V 0.01
I –1.14
VI –1.12
V
IV –50
V
V
–1.18
50
50
300
–1.22
–1.24
+500
V3
V 40
V
IV –1.2
IV 2.0
V
IV 100
V
V
V
V
V
20.48
2.5
15
110
27
6
28
2
2
+2
3.0
VI –1.0
VI
VI
VI
V
IV 0.5
IV 0.8
IV 1.8
IV 2.0
IV 2.5
2.8
–0.8
–1.7 –1.5
20
10
3
–0.3
1.2
1.7
V 70
V 72
V 68
V 68
AD9713B
All Grades
Min Typ
Max
0.5 2.5
5.0
1.0 5
8
0.01
–1.14
–1.12
–50
–1.18
50
50
300
–1.22
–1.24
+500
3
40
20.48
–1.2
2.0 2.5
15
80 100
27
7
28
2
2
+2
3.0
2.0
3
0.5 –0.3
0.8
1.8 1.2
2.0
2.5 1.7
2.8
0.8
20
600
70
72
68
68
Units
µA
µA
%
%
µA/°C
V
V
ppm/°C
µA
k
kHz
k
MHz
mA
V
k
pF
MSPS
ns
ns
pV-s
ns
ns
V
V
µA
µA
pF
ns
ns
ns
ns
ns
ns
dB
dB
dB
dB
–2– REV. B









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AD9712B Даташит, Описание, Даташиты
AD9712B/AD9713B
Parameter (Conditions)
Temp
Test
Level Min
AD9712B
All Grades
Typ
Max
AD9713B
All Grades
Min Typ
Max
Units
POWER SUPPLY13
Positive Supply Current (+5.0 V)
Negative Supply Current (–5.2 V)14
Nominal Power Dissipation
Power Supply Rejection Radio (PSRR)15
+25°C
Full
+25°C
Full
+25°C
+25°C
I
VI
I
VI
V
I
140 178
183
728
30 100
6 12
14
145 184
188
784
30 100
mA
mA
mA
mA
mW
µA/V
NOTES
1Measured as error in ratio of full-scale current to current through R SET (160 µA nominal); ratio is nominally 128.
2Full-scale variations among devices are higher when driving REFERENCE INPUT directly.
3Frequency at which the gain is flat ± 0.5 dB; RL = 50 ; 50% modulation at midscale.
4Based on IFS = 128 (VREF/RSET) when using internal amplifier.
5Data registered into DAC accurately at this rate; does not imply settling to 12-bit accuracy.
6Measured as voltage settling at midscale transition to ± 0.024%, RL = 50 .
7Measured as the time between the 50% point of the falling edge of LATCH ENABLE and the point where the output signal has left a 1 LSB error band
around its previous value.
8Peak glitch impulse is measured as the largest area under a single positive or negative transient.
9Measured with RL = 50 and DAC operating in latched mode.
10Data must remain stable for specified time prior to falling edge of LATCH ENABLE signal.
11Data must remain stable for specified time after rising edge of LATCH ENABLE signal.
12SFDR is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window, which is
centered at the fundamental frequency and covers the indicated span.
13Supply voltages should remain stable within ± 5% for normal operation.
14108 mA typ on Digital –VS, 37 mA typ on Analog –VS.
15Measured at ± 5% of +VS (AD9713B only) and –VS (AD9712B or AD9713B) using external reference.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
Positive Supply Voltage (+VS) (AD9713B Only) . . . . . . . +6 V
Negative Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . . –7 V
Analog-to-Digital Ground Voltage Differential . . . . . . . . 0.5 V
Digital Input Voltages (D1–D12, LATCH ENABLE)
AD9712B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to –VS
AD9713B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +VS
Internal Reference Output Current . . . . . . . . . . . . . . . . 500 µA
Control Amplifier Input Voltage Range . . . . . . . . . 0 V to –4 V
Control Amplifier Output Current . . . . . . . . . . . . . . . ± 2.5 mA
Reference Input Voltage Range (VREF) . . . . . . . . . . . 0 V to –VS
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
AD9712B/AD9713BAN/AP/BN/BP . . . . . . . –25°C to +85°C
AD9712B/AD9713BSE/SQ/TE/TQ . . . . . . –55°C to +125°C
Maximum Junction Temperature2
AD9712B/AD9713BAN/AP/BN/BP . . . . . . . . . . . . . +150°C
AD9712B/AD9713BSE/SQ/TE/TQ . . . . . . . . . . . . . +175°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Model
AD9712BAN
AD9712BBN
AD9712BAP
AD9712BBP
AD9712BSQ/883B
AD9712BSE/883B
AD9712BTQ/883B
AD9712BTE/883B
AD9713BAN
AD9713BBN
AD9713BAP
AD9713BBP
AD9713BSQ/883B
AD9713BSE/883B
AD9713BTQ/883B
AD9713BTE/883B
ORDERING GUIDE
Temperature
Range
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Package
Description
Package
Option
28-Pin PDIP
28-Pin PDIP
28-Pin PLCC
28-Pin PLCC
28-Pin Cerdip
28-Pin LCC
28-Pin Cerdip
28-Pin LCC
28-Pin PDIP
28-Pin PDIP
28-Pin PLCC
28-Pin PLCC
28-Pin Cerdip
28-Pin LCC
28-Pin Cerdip
28-Pin LCC
N-28
N-28
P-28A
P-28A
Q-28
E-28A
Q-28
E-28A
N-28
N-28
P-28A
P-28A
Q-28
E-28A
Q-28
E-28A
NOTES
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2Typical thermal impedances with parts soldered in place: 28-pin plastic DIP:
θJA = 37°C/W, θJC = 10°C/W; 28-pin PLCC: θJA = 44°C/W, θJC = 14°C/W;
Cerdip: θJA = 32°C/W, θJC = 10°C/W; LCC: θJA = 41°C/W, θJC = 13°C/W. No air
flow.
EXPLANATION OF TEST LEVELS
Test Level
I – 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% tested at +25°C. 100% production
tested at temperature extremes for extended tempera-
ture devices; sample tested at temperature extremes for
commercial/industrial devices.
REV. B
–3–










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