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PDF AL1201 Data sheet ( Hoja de datos )
| Número de pieza | AL1201 | |
| Descripción | stereo DAC | |
| Fabricantes | ETC | |
| Logotipo |  |
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We make the parts that set creative people free™
General Description
The AL1201 stereo DAC is a high
performance 24-bit digital to analog audio
converter. Dynamic range is 107dB (A-
weighted). The sensible pinout and easy
user interface are unprecedented. The part
contains an internal high quality phase-
locked loop that eliminates the need for
external high frequency clocks.
Features
G 24 bit conversion
G 107dB dynamic range (A-wt)
G .003% THD at full scale output
G linear phase analog outputs
G 128x over sampling, 5th order 1 bit ∆-Σ
modulator
G 2nd order switched cap filter and 2nd
order continuous-time filter on chip
G sample rate variable 24kHz-55kHz
G selectable deemphasis (15us/50µs at
Fs=44.1kHz)
G total power consumption 170mW
(Fs=48kHz)
G internal PLL derives all necessary timing
signals from external Fs clock
G serial input bit-rate, selectable 32/24
bits/frame
G full scale differential output = +/-4V
([OUT+]-[OUT-])
G 5V operation
OUTL-
OUTR-
OUTL+
OUTR+
AGND
MID
REF+
VA
REF-
AGND
VD DGND
DIN DEM
FORMAT
WDCLK
16 pin SOIC
150 mils wide
Alesis Semiconductor
DS1201-0702
12555 Jefferson Blvd., Suite 285
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
1 page  
System Description
Serial Interface and Timing
The AL1201 receives its 2’s complement
serial data in a standard MSB-first format.
Two bit-rates are allowed for. The 32
bits/frame (FORMAT low) is suitable for use
in systems where a 256Fs master clock is
present. The 24 bits/frame (FORMAT high)
is convenient when interfacing with systems
where a 384Fs clock is present.
The input sample period is defined between
rising edges of wordclock (WDCLK) input.
Nominally, this is a 50% duty-cycle clock at
frequency Fs, but it can be a pulse with
Ts/256 < pulse-width < Ts (255/256);
Ts=1/Fs. Left channel data is presented to
the AL1201 with rising edge of WDCLK, and
right channel data is presented Ts/2
seconds later (when WDCLK falls if 50%
duty cycle).
The serial bits are clocked into the AL1201
input registers on the falling edge of an
internally generated bit clock (rising edge
aligned with rising edge of WDCLK) that
runs at 64Fs when FORMAT is low (32
bits/frame), or 48Fs when FORMAT is high
(24 bits/frame). The input data should be
valid +/-100ns from the falling edge of this
internally generated clock. See timing
diagram next page.
Input Logic Levels
The AL1201 can properly receive input
logical ‘1’ voltages of .55VD. This means the
AL1201 can interface directly with logic
signals supplied from 3.3V systems. No
special interface circuitry is required.
Internal Phase-Locked Loop (PLL)
The AL1201 contains an internal PLL that
locks to the rising edge of WDCLK and
produces all necessary high frequency
clocks and timing signals to operate the
device. This high quality PLL will reject any
high-frequency jitter on the incoming
wordclock (jitter rejection corner approx.
4kHz).
The PLL allows a simplified user interface
and eliminates the need of running high
frequency clocks on PCB traces to the part.
This reduces unwanted RF noise and
coupling problems that can occur when
these clocks are required as input pins for a
device.
Alesis Semiconductor
DS1201-0702
12555 Jefferson Blvd., Suite 285
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
-5-
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet AL1201.PDF ] | |
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