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BH16899DGG PDF даташит

Спецификация BH16899DGG изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «18-bit latched transceiver with 16-bit parity generator/checker 3-State».

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Номер произв BH16899DGG
Описание 18-bit latched transceiver with 16-bit parity generator/checker 3-State
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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BH16899DGG Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74ABT16899
74ABTH16899
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
Product specification
Supersedes data of 1997 Mar 28
IC23 Data Handbook
1998 Feb 25
Philips
Semiconductors









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BH16899DGG Даташит, Описание, Даташиты
Philips Semiconductors
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
Product specification
74ABT16899
74ABTH16899
FEATURES
Symmetrical (A and B bus functions are identical)
Selectable generate parity or ”feed-through” parity for A-to-B and
B-to-A directions
Independent transparent latches for A-to-B and B-to-A directions
Selectable ODD/EVEN parity
Continuously checks parity of both A bus and B bus latches as
ERRA and ERRB
Open-collector ERR output
Ability to simultaneously generate and check parity
Can simultaneously read/latch A and B bus data
Output capability: +64 mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power up 3-State
Power-up reset
Live insertion/extraction permitted
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
DESCRIPTION
The 74ABT/H16899 is a 16-bit to 16-bit parity transceiver with
separate transparent latches for the A bus and B bus. Either bus
can generate or check parity. The parity bit can be fed-through with
no change or the generated parity can be substituted with the SEL
input.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
tPLH
tPHL
CIN
CI/O
ICCZ
ICCL
Propagation delay
An to Bn or Bn to An
Propagation delay
An to ERRA
Input capacitance
Output capacitance
Quiescent supply current
Parity error checking of the A and B bus latches is continuously
provided with ERRA and ERRB, even with both buses in 3-State.
The 74ABT/H16899 features independent latch enables for the A
and B bus latches, a select pin for ODD/EVEN parity, and separate
error signal output pins for checking parity.
FUNCTIONAL DESCRIPTION
The 74ABT/H16899 has three principal modes of operation which
are outlined below. All modes apply to both the A-to-B and B-to-A
directions.
Transparent latch, Generate parity, Check A and B bus parity:
Bus A (B) communicates to Bus B (A), parity is generated and
passed on to the B (A) Bus as BPAR (APAR). If LEA and LEB are
High and the Mode Select (SEL) is Low, the parity generated from
A0-A7 and B0-B7 can be checked and monitored by ERRA and
ERRB. (Fault detection on both input and output buses.)
Transparent latch, Feed-through parity, Check A and B bus
parity:
Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL
is High. Parity is still generated and checked as ERRA and ERRB
and can be used as an interrupt to signal a data/parity bit error to the
CPU.
Latched input, Generate/Feed-through parity, Check A (and B)
bus parity:
Independent latch enables (LEA and LEB) allow other permutations
of:
Transparent latch / 1 bus latched / both buses latched
Feed-through parity / generate parity
Check in bus parity / check out bus parity / check in and out bus
parity
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
CL = 50pF; VCC = 5V
VI = 0V or VCC
Outputs disabled; VO = 0V or VCC
Outputs disabled; VCC =5.5V
Output Low; VCC = 5.5V
TYPICAL UNIT
2.7 ns
5.0 ns
4 pF
7 pF
500 µA
10.5 mA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ABT16899 DL
–40°C to +85°C
74ABT16899 DGG
–40°C to +85°C
74ABTH16899 DL
–40°C to +85°C
74ABTH16899 DGG
NORTH AMERICA
BT16899 DL
BT16899 DGG
BH16899 DL
BH16899 DGG
DWG NUMBER
SOT371-1
SOT364-1
SOT371-1
SOT364-1
1998 Feb 25
2 853-1960 19018









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BH16899DGG Даташит, Описание, Даташиты
Philips Semiconductors
18-bit latched transceiver with 16-bit
parity generator/checker (3-State)
PIN CONFIGURATION
ODD/EVEN
OEA
1A0
GND
1A1
1A2
1A3
1A4
VCC
1A5
1A6
1A7
1APAR
1ERRA
GND
2ERRA
2APAR
2A7
2A6
2A5
VCC
2A4
2A3
2A2
2A1
GND
2A0
LEB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN DESCRIPTION
SYMBOL
1A0 - 1A7
2A0 - 2A7
1B0 - 1B7
2B0 - 2B7
1APAR
2APAR
1BPAR
2BPAR
ODD/EVEN
OEA, OEB
SEL
LEA, LEB
1ERRA, 1ERRB
2ERRA, 2ERRB
GND
VCC
1998 Feb 25
56 SEL
55 LEA
54 1B0
53 GND
52 1B1
51 1B2
50 1B3
49 1B4
48 VCC
47 1B5
46 1B6
45 1B7
44 1BPAR
43 1ERRB
42 GND
41 2ERRB
40 2BPAR
39 2B7
38 2B6
37 2B5
36 VCC
35 2B4
34 2B3
33 2B2
32 2B1
31 GND
30 2B0
29 OEB
SH00082
PIN
NUMBER
3, 5, 6, 7, 8, 10, 11, 12
27, 25, 24, 23, 22, 20, 19, 18
54, 52, 51, 50, 49, 47, 46, 45
30, 32, 33, 34, 35, 37, 38, 39
13, 17
44, 40
1
2, 29
56
55, 28
14, 43,
16, 41
4, 15, 26, 31, 42, 53
9, 21, 36, 48
3
Product specification
74ABT16899
74ABTH16899
NAME AND FUNCTION
Latched A bus 3-State inputs/outputs
Latched B bus 3-State inputs/outputs
A bus parity 3-State input
B bus parity 3-State input
Parity select input (Low for EVEN parity)
Output enable inputs (gate A to B,
B to A)
Mode select input (Low for generate)
Latch enable inputs (transparent High)
Error signal outputs (active-Low)
Ground (0V)
Positive supply voltage










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