BSH103 PDF даташит
Спецификация BSH103 изготовлена «NXP Semiconductors» и имеет функцию, называемую «N-channel enhancement mode MOS transistor». |
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Детали детали
Номер произв | BSH103 |
Описание | N-channel enhancement mode MOS transistor |
Производители | NXP Semiconductors |
логотип |
12 Pages
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DISCRETE SEMICONDUCTORS
DATA SHEET
andbook, halfpage
M3D088
BSH103
N-channel enhancement mode
MOS transistor
Product specification
Supersedes data of 1998 Jan 30
File under Discrete Semiconductors, SC13b
1998 Feb 11
No Preview Available ! |
Philips Semiconductors
N-channel enhancement mode
MOS transistor
Product specification
BSH103
FEATURES
• Very low threshold
• High-speed switching
• No secondary breakdown
• Direct interface to C-MOS, TTL etc.
PINNING - SOT23
PIN SYMBOL
1g
2s
3d
DESCRIPTION
gate
source
drain
APPLICATIONS
• Power management
• DC to DC converters
• Battery powered applications
• ‘Glue-logic’; interface between logic blocks and/or
periphery
• General purpose switch.
DESCRIPTION
N-channel enhancement mode MOS transistor in a SOT23
SMD package.
handbook, halfpage
3
d
g
1
Top view
2
MAM273
s
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
VDS
VSD
VGS
VGSth
ID
RDSon
Ptot
PARAMETERS
drain-source voltage (DC)
source-drain diode forward voltage
gate-source voltage (DC)
gate-source threshold voltage
drain current (DC)
drain-source on-state resistance
total power dissipation
CONDITIONS
VGD = 0; IS = 0.5 A
VDS = VGS; ID = 1 mA
Ts = 80 °C
VGS = 2.5 V; ID = 0.5 A
Ts = 80 °C
MIN.
−
−
−
0.4
−
−
−
MAX.
30
1
±8
−
0.85
0.5
0.5
UNIT
V
V
V
V
A
Ω
W
CAUTION
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
1998 Feb 11
2
No Preview Available ! |
Philips Semiconductors
N-channel enhancement mode
MOS transistor
Product specification
BSH103
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
VDS drain-source voltage (DC)
VGS gate-source voltage (DC)
ID drain current (DC)
IDM peak drain current
Ptot total power dissipation
Tstg storage temperature
Tj operating junction temperature
Source-drain diode
IS source current (DC)
ISM peak pulsed source current
CONDITIONS
Ts = 80 °C; note 1
note 2
Ts = 80 °C
Tamb = 25 °C; note 3
Tamb = 25 °C; note 4
Ts = 80 °C
note 2
MIN.
−
−
−
−
−
−
−
−55
−55
−
−
Notes
1. Ts is the temperature at the soldering point of the drain lead.
2. Pulse width and duty cycle limited by maximum junction temperature.
3. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 27.5 K/W.
4. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W.
MAX.
30
±8
0.85
3.4
0.5
0.75
0.54
+150
+150
0.5
2
UNIT
V
V
A
A
W
W
W
°C
°C
A
A
0.6
handbook, halfpage
Ptot
(W)
0.4
MGM190
0.2
0
0 40 80 120 160
Ts (°C)
Fig.2 Power derating curve.
1998 Feb 11
handbook,1h0alfpage
IDS
(A)
1
(1)
MBK502
(2)
10−1
P
10−2
δ=
tp
T
10−130−1
tp
T
1
t
DC
10 VDS (V) 102
δ = 0.01; Ts = 80 °C.
(1) RDSon limitation.
(2) Pulsed.
Fig.3 SOAR.
3
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