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MPC973 PDF даташит

Спецификация MPC973 изготовлена ​​​​«Motorola Semiconductors» и имеет функцию, называемую «LOW VOLTAGE PLL CLOCK DRIVER».

Детали детали

Номер произв MPC973
Описание LOW VOLTAGE PLL CLOCK DRIVER
Производители Motorola Semiconductors
логотип Motorola Semiconductors логотип 

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MPC973 Даташит, Описание, Даташиты
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage PLL Clock Driver
The MPC972/973 are 3.3V compatible, PLL based clock driver
devices targeted for high performance CISC or RISC processor based
systems. With output frequencies of up to 125MHz and skews of 550ps
the MPC972/973 are ideally suited for most synchronous systems. The
devices offer twelve low skew outputs plus a feedback and sync output for
added flexibility and ease of system implementation.
Fully Integrated PLL
Output Frequency up to 125MHz
Compatible with PowerPCand PentiumMicroprocessors
TQFP Packaging
3.3V VCC
± 100ps Typical Cycle–to–Cycle Jitter
MPC972
MPC973
LOW VOLTAGE
PLL CLOCK DRIVER
The MPC972/973 features an extensive level of frequency
programmability between the 12 outputs as well as the input vs output
relationships. Using the select lines output frequency ratios of 1:1, 2:1,
3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be
realized by pulsing low one clock edge prior to the coincident edges of the
Qa and Qc outputs. The Sync output will indicate when the coincident
rising edges of the above relationships will occur. The selectability of the
feedback frequency is independent of the output frequencies, this allows
for very flexible programming of the input reference vs output frequency
relationship. The output frequencies can be either odd or even multiples
of the input reference. In addition the output frequency can be less than
the input frequency for applications where a frequency needs to be
reduced by a non–binary factor. The Power–On Reset ensures proper
programming if the frequency select pins are set at power up. If the
fselFB2 pin is held high, it may be necessary to apply a reset after
power–up to ensure synchronization between the QFB output and the
other outputs. The internal power–on reset is designed to provide this
function, but with power–up conditions being system dependent, it is
difficult to guarantee. All other conditions of the fsel pins will automatically
synchronize during PLL lock acquisition.
FA SUFFIX
52–LEAD TQFP PACKAGE
CASE 848D-03
The MPC972/973 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system
debug as well as provide unique opportunities for system power down schemes to meet the requirements of “green” class
machines. The MPC972 allows for the enabling of each output independently via a serial input port. When disabled or “frozen”
the outputs will be locked in the “LOW” state, however the internal state machines will continue to run. Therefore when “unfrozen”
the outputs will activate synchronous and in phase with those outputs which were not frozen. The freezing and unfreezing of
outputs occurs only when they are already in the “LOW” state, thus the possibility of runt pulse generation is eliminated. A
power-on reset will ensure that upon power up all of the outputs will be active. Note that all of the control inputs on the
MPC972/973 have internal pull–up resistors.
The MPC972/973 is fully 3.3V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL
compatible levels while the outputs provide LVCMOS levels with the capability to drive 50transmission lines. For series
terminated lines each MPC972/973 output can drive two 50lines in parallel thus effectively doubling the fanout of the device.
The MPC972/973 can consume significant power in some configurations. Users are encouraged to review Application Note
AN1545/D in the Timing Solutions book (BR1333/D) for a discussion on the thermal issues with the MPC family of clock drivers.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
8/97
© Motorola, Inc. 1997
1
REV 1









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MPC973 Даташит, Описание, Даташиты
MPC972 MPC973
fselb1
fselb0
fsela1
fsela0
Qa3
VCCO
Qa2
GNDO
Qa1
VCCO
Qa0
GNDO
VCO_Sel
39 38 37 36 35 34 33 32 31 30 29 28 27
40 26
41 25
42 24
43 23
44 22
45 21
46
MPC972/
20
MPC973
47 19
48 18
49 17
50 16
51 15
52 14
1 2 3 4 5 6 7 8 9 10 11 12 13
fselFB1
QSync
GNDO
Qc0
VCCO
Qc1
fselc0
fselc1
Qc2
VCCO
Qc3
GNDO
Inv_Clk
Figure 1. 52–Lead Pinout (Top View)
FUNCTION TABLE 1
fsela1
fsela0
Qa
fselb1
fselb0
Qb
fselc1
fselc0
Qc
0 0 ÷4 0 0 ÷4 0 0 ÷2
0 1 ÷6 0 1 ÷6 0 1 ÷4
1 0 ÷8 1 0 ÷8 1 0 ÷6
1 1 ÷12 1 1 ÷10 1 1 ÷8
FUNCTION TABLE 2
fselFB2
fselFB1
00
00
01
01
10
10
11
11
fselFB0
0
1
0
1
0
1
0
1
QFB
÷4
÷6
÷8
÷10
÷8
÷12
÷16
÷20
FUNCTION TABLE 3
Control Pin
Logic ‘0’
VCO_Sel
Ref_Sel
TCLK_Sel
PLL_En
MR/OE
Inv_Clk
VCO/2
TCLK
TCLK0
Bypass PLL
Master Reset/Output Hi–Z
Non–Inverted Qc2, Qc3
Logic ‘1’
VCO
Xtal (PECL)
TCLK1
Enable PLL
Enable Outputs
Inverted Qc2, Qc3
MOTOROLA
2 TIMING SOLUTIONS
BR1333 — Rev 6









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MPC973 Даташит, Описание, Даташиты
972 OPTION
xtal1
xtal2
VCO_Sel
PLL_En
REF_SEL
TCLK0
TCLK1
TCLK_Sel
Ext_FB
0
1
973 OPTION
PCLK
PCLK
fselFB2
MR/OE
POWER-ON
RESET
fsela0:1
fselb0:1
fselc0:1
fselFB0:1
Frz_Clk
Frz_Data
Inv_Clk
PHASE
DETECTOR
LPF
VCO
0
1
÷4, ÷6, ÷8, ÷12
÷4, ÷6, ÷8, ÷10
÷2, ÷4, ÷6, ÷8
2
÷4, ÷6, ÷8, ÷10
0
2 ÷2 1
2 Sync Pulse
2
Data Generator
Output Disable
Circuitry
12
Figure 2. Logic Diagram
MPC972 MPC973
DQ
Sync
Frz
DQ
Sync
Frz
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
Qc0
Qc1
Qc2
Qc3
QFB
QSync
TIMING SOLUTIONS
BR1333 — Rev 6
3
MOTOROLA










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