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PDF AK4113 Data sheet ( Hoja de datos )
| Número de pieza | AK4113 | |
| Descripción | 192kHz 24bit DIR | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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ASAHI KASEI
[AK4113]
AK4113
192kHz 24bit DIR with 6:1 Selector
GENERAL DESCRIPTION
The AK4113 is a 24-bit stereo digital audio receiver that supports sampling rates up to 216kHz. The
channel status bits decoder supports both consumer and professional modes. The AK4113 automatically
detects non-PCM bit streams such as Dolby Digital, MPEG etc. When combined with the multi channel
codec (AK4626 or AK4628), the two chips provide a system solution for Dolby Digital applications.
Control of AK4113 is achieved though a µP or pin strapping (parallel mode). It is packaged in a
space-saving 30-pin VSOP.
* Dolby Digital is a trademark of Dolby Laboratories.
FEATURES
AES/EBU, IEC60958, S/PDIF, EIAJ CP1201 Compatible
Low Jitter Analog PLL
PLL Lock Range: 8k ∼ 216kHz
Clock source: PLL or X'tal
6-channel Receiver Input and 1-channel Transmission Output (Through
output)
Auxiliary Digital Input
De-emphasis for 32kHz, 44.1kHz and 48kHz
Detection Functions
- Non-PCM Bit Stream Detection
- DTS-CD Bit Stream Detection
- Sampling Frequency Detection
(8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz,
64kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz)
- Unlock & Parity Error Detection
- Validity Detection
- DAT Start ID Detection
Up to 24bit Audio Data Format
Audio Interface: Master or Slave Mode
40-bit Channel Status Buffer
Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream
Q-subcode Buffer for CD bit stream
Serial µP Interface: I2C (max. 400kHz) or 4-wire
Two Master Clock Outputs: 64fs/128fs/256fs/512fs
Operating Voltage: 2.7 to 3.6V with 5V Logic Tolerance
Small Package: 30pin VSOP
Ta: - 40 ∼ 85°C
MS0349-E-02
-1-
2005/08
1 page  
ASAHI KASEI
[AK4113]
No. Pin Name
I/O
Function
OCKS1
28 CCLK
I Output Clock Select #1 Pin in parallel control mode
I Control Data Clock Pin in serial control mode, I2C pin = “L”
SCL I Control Data Clock Pin in serial control mode, I2C pin = “H”
CM1
I Master Clock Operation Mode #1 Pin in parallel control mode
29 CDTI
SDA
I Control Data Input Pin in serial control mode, I2C pin = “L”
I/O Control Data Pin in serial control mode, I2C pin = “H”
CM0
30 CDTO
CAD1
I Master Clock Operation Mode #0 Pin in parallel control mode
O Control Data Output Pin in serial control mode
I Chip Address #1 Pin in serial control mode, I2C pin = “H”
Note 1. Do not allow digital input pins expect internal biased pins (RX1-6 pins) to float.
Handling of Unused Pin
The unused I/O pin should be processed appropriately as below.
Classification
Analog Input
Digital Input
Digital Output
Pin Name
RX1, RX2/DIF0, RX3/DIF1, RX4/DIF2,
RX5, RX6/IPS
RX1, RX5
DAUX, XTI
V/TX, XTO, INT0, INT1, MCKO1, MCKO2
I2C/FS96
CAD1/CDTO/CM0
Setting
These pins should be open in serial control mode.
These pins should be open in parallel control
mode.
These pins should be connected to DVSS.
These pins should be open.
This pin should be open in parallel control mode.
This pin should be open in serial control mode and
4-wire mode (I2C pin = “L”).
MS0349-E-02
-5-
2005/08
5 Page 
ASAHI KASEI
Timing Diagram
XTI
MCKO1
MCKO2
LRCK
LRCK
BICK
SDTO
DAUX
[AK4113]
1/fECLK
tECLKH
tECLKL
1/fMCK1
VIH
VIL
dECLK = tECLKH x fECLK x 100
= tECLKL x fECLK x 100
tMCKH1
tMCKL1
1/fMCK2
50%DVDD
dMCK1 = tMCKH1 x fMCK1 x 100
= tMCKL1 x fMCK1 x 100
50%DVDD
tMCKH2
tMCKL2
1/fs
dMCK2 = tMCKH2 x fMCK2 x 100
= tMCKL2 x fMCK2 x 100
tLRH
tLRL
Figure 3. Clock Timing
VIH
VIL
dLCK = tLRH x fs x 100
= tLRL x fs x 100
tBLR tLRB
tBCK
tBCKL tBCKH
tLRM
tBSD
tDXS tDXH
VIH
VIL
VIH
VIL
50%DVDD
VIH
VIL
Figure 4. Serial Interface Timing (Slave Mode)
MS0349-E-02
- 11 -
2005/08
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK4113.PDF ] | |
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