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PDF MR25H256A Data sheet ( Hoja de datos )
| Número de pieza | MR25H256A | |
| Descripción | 256Kb Serial SPI MRAM | |
| Fabricantes | Everspin Technologies | |
| Logotipo |  |
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MR25H256 / MR25H256A
FEATURES
• No write delays
• Unlimited write endurance
• Data retention greater than 20 years
• Automatic data protection on power loss
• Block write protection
• Fast, simple SPI interface with up to 40 MHz clock rate
• 2.7 to 3.6 Volt power supply range
• Low current sleep mode
• Industrial and Automotive Grade 1 and Grade 3 tempera-
tures
• Available in 8-DFN or 8-DFN Small Flag RoHS-compliant
package.
• Direct replacement for serial EEPROM, Flash, FeRAM
• Industrial Grade and AEC-Q100 Grade 1 and Grade 3 options
• Moisture Sensitivity MSL-3
256Kb Serial SPI MRAM
8-DFN
Small Flag 8-DFN
RoHS
Product Versions and Options
MR25H256A has been released for mass production and is recommended for all new designs.
MR25H256 remains in mass production but will be subject to eventual phase out and end of life
and is not recommended for new designs.Both versions have the same specifications.
MR25H256A Product Options
Grade
Industrial
Automotive AEC-Q100 Grade 3
Automotive AEC-Q100 Grade 1
Temperature Package
-40 to +85 C 8-DFN Small Flag
-40 to +85 C 8-DFN Small Flag
-40 to +125 C 8-DFN Small Flag
MR25H256 Product Options (Not recommended for new designs)
Grade
Temperature Package
Industrial
-40 to +85 C
8-DFN Small Flag
8-DFN
Automotive AEC-Q100 Grade 1
-40 to +125 C
8-DFN Small Flag
8-DFN
Copyright © 2017 Everspin Technologies
1 MR25H256 / MR25H256A Rev. 1.4, 2/2017
1 page  
MR25H256 / MR25H256A
DEVICE PIN ASSIGNMENT
Figure 3 – Pin Diagram All 8-DFN Packages
CS 1
SO 2
WP 3
VSS 4
8 VDD
7 HOLD
6 SCK
5 SI
Top View
Table 1 – Pin Functions All 8-DFN Packages
Signal Name Pin I/O
Function
CS
1 Input
Chip Select
Description
An active low chip select for the serial MRAM. When chip select is high, the
memory is powered down to minimize standby power, inputs are ignored
and the serial output pin is Hi-Z. Multiple serial memories can share a com-
mon set of data pins by using a unique chip select for each memory.
SO
WP
VSS
SI
SCK
HOLD
2 Output
3 Input
4 Supply
5 Input
6 Input
7 Input
Serial Output
Write Protect
Ground
Serial Input
Serial Clock
Hold
The data output pin is driven during a read operation and remains Hi-Z at
all other times. SO is Hi-Z when HOLD is low. Data transitions on the data
output occur on the falling edge of SCK.
A low on the write protect input prevents write operations to the Status
Register.
Power supply ground pin.
All data is input to the device through this pin. This pin is sampled on the
rising edge of SCK and ignored at other times. SI can be tied to SO to create
a single bidirectional data bus if desired.
Synchronizes the operation of the MRAM. The clock can operate up to 40
MHz to shift commands, address, and data into the memory. Inputs are
captured on the rising edge of clock. Data outputs from the MRAM occur
on the falling edge of clock. The serial MRAM supports both SPI Mode 0
(CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is
normally low. In Mode 3, the clock is normally high. Memory operation is
static so the clock can be stopped at any time.
A low on the Hold pin interrupts a memory operation for another task.
When HOLD is low, the current operation is suspended. The device will
ignore transitions on the CS and SCK when HOLD is low. All transitions of
HOLD must occur while CS is low.
VDD 8 Supply Power Supply Power supply voltage from +2.7 to +3.6 volts.
Copyright © 2017 Everspin Technologies
5 MR25H256 / MR25H256A Rev. 1.4, 2/2017
5 Page 
MR25H256 / MR25H256A
Write Data Bytes (WRITE)
The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by
the 16-bit address. Only address bits 0-14 are decoded by the memory. The data bytes are written sequen-
tially in memory until the write operation is terminated by bringing CS high. The entire memory can be
written in a single command. The address counter will roll over to 0000h when the address reaches the top
of memory.
Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock
speed without write delays or data polling. Back to back WRITE commands to any random location in mem-
ory can be executed without write delay. MRAM is a random access memory rather than a page, sector, or
block organized memory making it ideal for both program and data storage.
The WRITE command is entered by driving CS low, sending the command code, and then sequential write
data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS
high.
Figure 9 – WRITE
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30 31
Instruction (02h)
16-Bit Address
SI
0 0 0 0 0 0 1 0 X 14 13
321076543210
MSB MSB
SO High Impedance
CS
SCK
SI
SO
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Mode 3
Mode 0
Data Byte 2
Data Byte 3
7654321076543210
MSB
High Impedance
Data Byte N
76543210
MSB
Copyright © 2017 Everspin Technologies
11 MR25H256 / MR25H256A Rev. 1.4, 2/2017
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MR25H256A.PDF ] | |
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