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TS86101G2B PDF даташит

Спецификация TS86101G2B изготовлена ​​​​«e2v» и имеет функцию, называемую «4:1 10-bit 1.2 Gsps MUXDAC».

Детали детали

Номер произв TS86101G2B
Описание 4:1 10-bit 1.2 Gsps MUXDAC
Производители e2v
логотип e2v логотип 

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TS86101G2B Даташит, Описание, Даташиты
TS86101G2B
4:1 10-bit 1.2 Gsps MUXDAC
Datasheet
Main Features
10-bit Resolution
1.2 Gsps Guaranteed Conversion Rate, 1.4 Gsps Typical
4:1 Integrated Parallel MUX
PECL/LVDS Differential Data and Clock Inputs
2 Vpp Differential Analog Output Swing
Output Impedance: 50Ω Single-ended, 100Ω Differential
Programmable DSP Clock
Power Up Reset for Easy Synchronization of Several DACs
Dual Power Supply: ±5V
CBGA 255 Package for = C and V Grades
CI-CGA 255 Package for M Grade
Evaluation Board TSEV86101G2BGL
Performance
Broadband
– NPR: 49 dB at Fs = 1.2 Gsps: 9.5 bits equivalent (20 MHz to 580 MHz Broadband Pattern, 25 MHz Notch Centered Around
250 MHz)
Single Tone
– SFDR Baseband (Full First Nyquist Zone):
70 dBFS at Fs = 1.0 Gsps
68 dBFS at Fs = 1.2 Gsps
– SFDR in Third Nyquist Zone
69 dBFS at Fs = 1.2 Gsps, Fout = 5 × Fs/4
> 60 dBFS at Fs = 1.2 Gsps, Fout = 5 × Fs/4 ±150 MHz (–12 dBm Constant Output Power over 300 MHz Instantaneous
Bandwidth)
Multi-tone
– Eight-tone IMD: 70 dBFS at Fs = 1.2 Gsps and 500 MHz Baseband
Eight Tones Ranging from 80 MHz to 517.5 MHz, 62.5 MHz Spacing
Total Power Dissipation = 3.6W
Applications
Direct Digital Synthesis (DDS) for Broadband Applications
Digital Beam Forming
Automatic Test Equipment (ATE)
Instrumentation: Arbitrary Waveform Generator
Screening
Temperature Range:
– C grade: 0°C < TC; TJ < 90°C
– V grade: –40°C < TC; TJ< 110°C
– M grade: –55°C < TC; TJ < 125°C
e2v semiconductors SAS 2009
Visit our website: www.e2v.com
for the latest version of the datasheet
0992D–BDC–04/09









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TS86101G2B Даташит, Описание, Даташиты
TS86101G2B
1. Description
The TS86101G2B is a 10-bit 1.2 Gsps DAC with an integrated 4:1 multiplexer, allowing easy interfacing with standard
FPGAs. The enhanced linearity and Noise Power Ratio (NPR) performance (9.5 bits equivalent at 1.2 Gsps) over 550 MHz
instantaneous bandwidth make this product particularly suitable for high-end applications such as arbitrary waveform gen-
erators and broadband DDS systems.
2. Specifications
Table 2-1. Absolute Maximum Ratings
Parameter
Positive digital power supply
Negative digital power supply
Negative analog power supply
Maximum difference between negative supply voltages
Digital inputs
Port Y = A/B/C/D
Maximum difference digital inputs
Port Y = A/B/C/D
Data ready clock input
Maximum difference between D_CK_T and D_CK_F
Master clock input
Maximum difference between CW_IN_T and CW_IN_F
Digital shift select voltage
Maximum junction temperature
Storage temperature
Lead temperature
Symbol
VCCD
VEED
VEEA
VEED - VEEA
<Y0_T; Y9_T> or
<Y0_F; Y9_F>
<Y0_T; Y9_T>
<Y0_F; Y9_F>
D_CK_T, D_CK_F
D_CK_T, D_CK_F
CW_IN_T, CW_IN_F
CW_IN_T, CW_IN_F
CS
TJ
Tstg
Tballs
Comments
Value
GND to 6.0
–6.0 to GND
–6.0 to GND
0.7
VIL > –0.25
VIH < 5.5
VIH - VIL < 1.4
VIL > –0.25
VIH < 5.5
VIH - VIL < 1.4
VIL > –3.5
VIH < 0.75
VIH - VIL < 1.2
GND to VCCD
135
–65 to 150
250 (during 10s max.)
Unit
V
V
V
V
V
Vp
V
Vp
V
Vp
V
°C
°C
°C
Notes:
1. Maximum ratings are limiting values only (referenced to GND = 0V), and are to be applied individually, while other parame-
ters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability. The use of a
thermal heat sink is mandatory (refer to “Thermal and Moisture Characteristics” on page 36.)
2. Maximum ratings enable active inputs with MUXDAC power off.
3. Maximum ratings enable floating inputs with MUXDAC power on.
2
0992D–BDC–04/09
e2v semiconductors SAS 2009









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TS86101G2B Даташит, Описание, Даташиты
TS86101G2B
Table 2-2. Recommended Conditions of Use
Parameter
Symbol
Comments
Typ Unit
Positive digital power supply
Negative digital power supply(1)
Negative analog power supply(1)
Differential digital inputs
Port Y = A, B, C, D
VIH
VIL
Swing (on each single-ended input)
VCCD
VEED
VEEA
<Y0_T; Y9_T>
<Y0_F; Y9_F>
5V
–5 V
–5 V
1.4 V
1.0 V
0.2 Vp
Differential data ready clock inputs
VIH
VIL
Swing (on each single-ended input)
D_CK_T
D_CK_F
1.4 V
1.0 V
0.2 Vp
Differential master clock inputs
Swing (on CW_IN_T)
CW_IN_T
CW_IN_F
Single-ended mode: master clock applied on
CW_IN_T through 10 nF AC capacitor.
CW_IN_F grounded through 10 nF AC capacitor
0.316
Vp
Master clock input power level
PCW_IN_T
PCW_IN_F
Single-ended mode
0 dBm
Operating temperature range
TC, TJ
Commercial “C” grade
Industrial “V” grade
Military “M” grade
0°C < TC;
TJ < 90°C
–40°C < TC;
TJ < 110°C
–55°C < TC;
TJ < 125°C
°C
Note:
1. VEAA and VEED are internally short circuited through the chip substrate (4Ω equivalent resistance between VEEA and VEED).
Therefore, VEEA and VEED must be externally driven by the same power supply source with VEEA and VEED board planes
short circuited, and power supply connected to the VEEA plane.
e2v semiconductors SAS 2009
0992D–BDC–04/09
3










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