AT84CS001 PDF даташит
Спецификация AT84CS001 изготовлена «e2v» и имеет функцию, называемую «10-bit 2.2 Gsps 1:4 DMUX». |
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Детали детали
Номер произв | AT84CS001 |
Описание | 10-bit 2.2 Gsps 1:4 DMUX |
Производители | e2v |
логотип |
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AT84CS001
10-bit 2.2 Gsps 1:4 DMUX
Datasheet
Features
• High-speed ADC Family Companion Chip
• Selectable 1:2 or 1:4 DMUX Ratio
• Power Consumption: 2.7W
• LVDS Compatible Differential Data and Clock Inputs (100Ω Terminated)
• LVDS Compatible Differential Data and Data Ready Outputs
• Staggered or Simultaneous Data Outputs
– 11th Bit = Ports A, B, C and D Clock in Staggered Mode
• Selectable Active Edge for Input and Output Clocks:
– Only Rising: CLK and DR Mode
– Rising and Falling: CLK/2 and DR/2 Mode
• Fine Tuning of Input Clock Path Delay
– Compensation of External Data and Clock Path Misalignment and Skews
– Once Tuned, Setting is Valid over Full Operating Frequency and Over Full Specified Temperature Range
• Additional 11th Bit (Example: for Out-of-range Bit)
• Built-in Self Test (BIST)
• Stand-alone Tunable Delay Cell
• Power Supplies: VCCD = 3.3V (Digital), VPLUSD = 2.5V (Outputs)
• Power Consumption Reduction Mode: 1.15W
• EBGA240 Package
Screening
• Temperature Range:
– - 40°C < TC; TJ < 110°C (Industrial Grade)
Applications
This DMUX enables users to process high-speed output data streams from fast analog-to-digital converters down to stan-
dard FPGA processor speed.
Description
The AT84CS001 is a monolithic high-speed demultiplexer, used to lower a 10-bit data stream of up to 2.2 Gsps guaranteed
rate by a selectable 4 or 2 ratio (a 1:8 ratio might be achieved by interleaving two DMUXes).
The DMUX is a companion chip designed to fit perfectly with all of e2v’s high-speed ADCs and is capable of tracking the
ADC’s output sampling rate over all operating frequency and temperature ranges.
Thanks to its LVDS buffers, this DMUX can easily be interfaced with standard high-speed FPGAs (100Ω differentially
terminated).
The AT84CS001 has the same footprint as e2v’s TS81102G0 DMUX, with a very similar pinout. Minimum re-design efforts
are required to use this low-power DMUX. An application note Migration from AT84AS008 to EV10AS008B reference 0810,
is available to assist in migrating from the TS81102G0 to the AT84CS001.
e2v semiconductors SAS 2009
Visit our website: www.e2v.com
for the latest version of the datasheet
0809E–BDC–05/09
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1. Block Diagram
Figure 1-1. Block Diagram
AT84CS001
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0809E–BDC–05/09
e2v semiconductors SAS 2009
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AT84CS001
2. Overview
The AT84CS001 is a monolithic high-speed demultiplexer (DMUX) using high-speed e2v technology.
It enables the user to lower a 10-bit stream of 2.2 Gsps maximum by a factor of two or four. One can
obtain a 1:8 ratio by using two interleaved AT84CS001 devices. The maximum input data rate is 2.2
Gsps in 1:4 ratio and 1.8 Gsps in 1:2 ratio.
The AT84CS001 DMUX is capable of processing an 11-bit data flow. The additional 11th bit (IOR, IORN)
might be connected for example to the out-of-range bit of a 10-bit ADC.
The input and output clocks as well as the input and output data are LVDS compatible. Digital inputs are
100Ω differentially terminated on chip. Digital output buffers shall be terminated by a 100Ω differential
ASIC load.
The improved architecture of the DMUX facilitates interfacing with high-speed ADCs operating at up to
2.2 Gsps. A tunable delay cell is integrated in serial with the clock input: it can be used to tune the delay
between the data and clock paths namely for high speed rates and in the case of misalignment or skews
between the external clock path and the data path. The delay is controlled by means of the CLKDACTRL
analog control input. The tunable delay ranges from -250 ps to 250 ps for CLKDACTRL varying from
VCCD/2 to (2 × VCCD)/3.
Two modes can be selected for the clock input (CLK and CLK/2) and the clock output (DR and DR/2):
• CLK and DR mode: Only the rising edges of the input (CLK,CLKN) and output (DR, DRN) clocks are
active. The input (or output) clock rate remains the same as the input or output data rate.
• CLK/2 and DR/2 mode: Both the rising and falling edges of the input (CLK,CLKN) and output (DR,
DRN) clocks are active. The input (or output) clock rate is half the input or output data rate.
The data outputs can be received at the DMUX output in two different modes:
• Staggered: even and odd bits are output with half a data period delay
• Simultaneous: even and odd bits are output at the same time
The AT84CS001 DMUX is started by the ASYNCRST control input that acts as a master asynchronous
reset for the device. Once reset, there is no loss of synchronization over an indefinite time period, there-
fore no additional incoming synchronous reset signal is required.
The power consumption of the AT84CS001 is 2.7W and can be reduced by approximately 60% of its
nominal value by means of the SLEEP control input.
A standalone delay cell is provided. It features a typical 550 ps tuning range (± 275 ps around the center
value of DACTRL analog control input).
A Built-in Self Test (BIST) is implemented for rapid debugging of the DMUX.
The AT84CS001 DMUX is a companion chip designed to fit perfectly with all of e2v’s high-speed ADCs.
e2v semiconductors SAS 2009
0809E–BDC–05/09
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Номер в каталоге | Описание | Производители |
AT84CS001 | 10-bit 2.2 Gsps 1:4 DMUX | e2v |
AT84CS001 | 10-BIT 1:2/4 2.2GHz LVDS DMUX | ATMEL Corporation |
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