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Спецификация 6501 изготовлена ​​​​«Commodore» и имеет функцию, называемую «ONE-CHIP MICROCOMPUTER».

Детали детали

Номер произв 6501
Описание ONE-CHIP MICROCOMPUTER
Производители Commodore
логотип Commodore логотип 

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6501 Даташит, Описание, Даташиты
, . .commodore
~ aarnlconduCl:ar group
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MPS
6500/1
ONE-CHIP
MICROCOMPUTER
8500/1 ONE-CHIP MICROCOMPUTER
INTRODucnoN
The MOS Technology 6500/1 Is a complete, high-performance 8-blt NMOS microcomputer on a single chip, and
Is totally upward/downward software compatible with all members of the 6500 family.
The 650011 consists of a 6502 CPU, an Internal clock oscillator, 2048 bytes of Read Only Memory (ROM), 64 bytes
of Random Access Memory (RAM) and flexible Interface circuitry. The· interface circuitry includes a 18-blt
programmable counter/latch with four operating modes, 32 bidirectional Input/output lines (Including two edge-
sensitive lines), five Interrupts and a counter I/O line.
PRODUCT SUPPORT
To allow prototype clrCl~lt development, Mos Tech-
nology offers a PROM compatible 64-pln Emulator de-
vice. This device provides all 650011 Interface lines
plus routing the address bus, data bus, and asso-
ciated control lines off the chip to be connected to
external memory.
Order
Number
ORDERING INFORMATION
Package Frequency Temperature
Type Option
Range
MPS65OOI1
Plastic 1 MHz
MCS6500/1 Ceramic 1 MHz
MPS65OOI1A Plastic 2 MHz
MCS65OOI1A Ceramic 2 MHz
MCS65OOI1E Emulator Device 1MHz
'MCS65OOI1EA Emulator Device 2MHz
O°C to 70°C
O°C to 70°C
O°C to 70°C
O°C to 70°C
Note: The RC frequency option is available only in the
1 MHz 6500/1.
XTU
)(flO
RES
Rgj
vee
vss
VRR
¢a;> PAO-PA7
¢a~ P8(H2B7
¢a ~ pc()'PC7
¢a::> POOPD7
CNTR
FEATURES
• 6502 CPU
-Software upward/downward compatibility
-Decimal or binary arithmetic modes
-13 addressing modes
-True direct and indirect indexing
-Memory addressable 110
• 2048 x 8 mask programmable ROM
• 64 x 8 static RAM
• 32 bi<iirectional TIL compatible 110 lines (4 ports)
• 1 bi<iirectional TIL compatible counter I/O line
• 16-bit programmable counter/latch with four
modes
-Interval Timer -Event Counter
-Pulse Generator -Pulse Width Measurement
• Five Interrupts
-Reset
-Non·maskable
-Two external edge sensitive
-Counter
• 1 of 3 frequency references
-Crystal -Clock -RC (resistor only)
• 4 MHz max crystal or clock external frequency
• 2 MHz or 1 MHz internal clock
• 1 /Ls minimum instruction execution
• N-channel, silicon gate, depletion load technology
• Single + 5V power supply
• 500 mW operating power
• Separate power pin for RAM
• 40 pin DIP
• 64 pin PROM compatible Emulator device
Interface Diagram
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6501 Даташит, Описание, Даташиты
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
Clock OIcIllator
The Clock Oscillator provides the basic timing
Signals used by the 6500/1 CPU. The reference fre-
quency Is provided by an external source, and can be
from a crystal, clock or RC network Input. The RC net·
work mode Is a mask option. The external frequency
can vary from 200 kHz to 4 MHz. The Internal Phase 2
(02) frequency Is one-half the external reference fre-
quency. A 4.7K ohm resistor will provide nominal 2
MHz oscillation and 1 MHz Internal operation In the
RC mask option (±35%).
TIming Control
The Timing Control Logic keeps track of the
specific Instructlo:1 cycle being executed. Each data
transfer which takes place between the registers Is
caused by decoding the contents of both the Instruc·
tlon Register and Timing Control Logic.
Program Counter
The 16-blt Program Counter provides the addresses
which step the CPU through sequential Instructions
In a program. The Program Counter Is Incremented
each time an instruction or data Is fetched from
memory.
Instruction Register and Decode
Instructions fetched from memory are gated onto
the Internal Data Bus. These Instructions are iatched
Into the Instruction Register then decoded, along with
timing and Interrupt Signals, to generate controi
Signals for the various registers.
ArIthmetic and Logic Unit (ALU)
All arithmetic and logic operations take place In the
ALU, including incrementing and decrementing Inter·
nal registers (except the Program Counter).
Accumulator
The accumulator Is a general purpose 8-blt register
that stores the results of most arithmetic and logic
operations. In addition, the accumulator usually con·
talns one of the two data words used In these opera·
tlons.
Index Registers
There are two 8-blt Index registers, X and Y. These
registers can be used for general purpose storage, or
as a displacement to modify the base address and
thus obtain a new effective address. Pre· or post·
indexing of Indirect addresses is possible.
Stack Pointer
The Stack Pointer is an 8-blt register. it Is automat·
ically incremented and decremented under control of
the CPU to perform stack manlpuiatlon under d~·
tlon of either the program or interrupts NMI and IRQ.
The stack allows simple Implementation of nested
subroutines and multiple level interrupts.
lNJV/
MPS
6500/1
/B/O/I Z C
,,'~.,'"=1 Carry Set
0= Carry CI••r
ITSZERO (Z)(1)
=1 Zero Result
l:= =o Non-Zero Result
INTERRUPT DISABLE (1) (2)
1 = IRQ Interrupt Disabled
o = IRQ Interrupt Enabled
DECIMAL MODE (D) (1)
=1 Decimal Mode
o = Binary Mode
BREAK COMMAND (B) (1)
=, = Break Command
o Not Break Command
OVERFLOW (0) (1)
1 = Overflow set
Q = Overflow Clear
NOTES:
(1) Not initialized by RES
(2) Set to Logic 1 by REs
NEGATIVE (N) (1)
1 = Negative Value
o = Positive Value
I
Processor Status Register
Processor Status Register
The 8-blt Processor Status Register contains seven
status flags. Some of the flags are controlled by the
program, others may be controlled both by the pro-
gram and the CPU. The 6500 Instruction set contains
a number of conditional branch Instructions which
are designed to allow testing of these flags.
Interrupt Logic
Interrue!..!9glc controls the sE!Cluenclng of three In·
terrupts; RES, ~ and !'RO. iRQ Is generated by any
one of three conditions: Counter Overflow, PAO
Positive Edge Detected, and PA1 Negative Edge De-
tected.
MEMORY
2048 x 8 ROM
The 2048 byte Read-Only Memory (ROM) contains
the program instructions and other fixed constants.
These program Instructions and constants are mask
programmed Into the ROM during fabrication of the
6500/1 device. The 650011 ROM is memory mapped
from 800 to FFF.
64 x 8 RAM
The 64 byte Random Access Memory (RAM) Is used
for read/write memory during system operation, and
contains the stack. This RAM is completely static in
operation and requires no clock or dynamic refresh. A
standby power pin, VRR, allows RAM memory to be
maintained on 10% of the operating power In the
event that VCC power Is lost.
In order to take advantage of efficient zero page ad·
dressing capabilities, the RAM is assigned memory
addresses 0 to 03F.
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6501 Даташит, Описание, Даташиты
MPS
8500/1
INPUTIOUTPUT
BIdirectional 110 Port,
The 650011 provides four 8-blt Input/output ports
(PA, PB, PC, and PO). Associated with the 110 ports
are four 8-blt registers located on page zero. See the
system memory map for specific addresses. Each 110
line Is Individually selectable as an Input or an output
without line grouping or port association restrictions.
An Internal active transistor drives each 110 line to
the low state. An Internal passive resistance pulls the
I/O lines to the high state, eliminating the need for ex-
ternal pull-up resistors.
An option Is available to delete the Internal pull-up
resistance on 8-blt port groups or on the CNTR line at
mask time. This option Is employed to permanently
assign an 8-blt port group to Input functions, to Inter-
face with CMOS drivers, or to Interface with external
pull-up devices.
Inputs
Inputs are enabled by setting the appropriate bit of
the 110 port to the high state (Logic 1). A low Input
signal causes a logic 0 to be read. A high Input signal
causes a logic 1 to be read. RES loads Logic 1 Into the
110 ports, thereby Initializing all 110 lines as Inputs.
Outputs
Outputs are set by loading the desired bit pattern
into the corresponding 110 ports. A Logic 1 selects a
high output; a Logic 0 selects a low output.
CONTROL REGISTER
The Control Register (CR) controls four Counter
operating modes and three maskable Interrupts. It
also reports the status of three Interrupt conditions.
There are five control bits and three status bits. The
control bits are set to Logic 1 or cleared to Logic 0 by
writing the desired state Into the respective bit posi-
tions. The Control Register Is cleared to Logic 0 by the
occurrence of RES.
76 5 4 3 2 1 0
~~~~~~rCl'~[~O[lE[~ll-'E-ICL~~ COUNTER MODE CONTROl (CMC1' CMCO!
=00 Inlernal Timer
=01 FtulseGeneralor
10= Even! Counter
1 1 11: Pulse Width Measurement
=.. _. ----~. - PAllNTEAAUPT ENABLE (AilE)
I Enabla PAllnlerrupl
0= Olsable PAlln18uupi
=--_.... --- PAC INTERRUPT ENABLE (AOIEI
1 Enable PAO Inlllrrupi
0= Disable PAO Inlertupl
- -- -- COUNTER INTERRUPT ENABLE (CIE)
1 ::I Enable Counler Interrupt
0= Ol5sbieCounier Inlerrupl
- - - -- PAl NEGATIVE EDGE DETECTED (A1EDI
=1 PA 1 Negalive Edge DelltCled
=o PA 1 Negali\18 Edge Not Oelecled
PAC POSITIVE EDGE DETECTED (AOEDI
=1 PAO PoSItive Edge Detected
=o PAO Positive Edge Nol Delecled
=-- - - COUNTER OVERFlOW (CTRO)
1 Counl8f Overflow Occurred
o = No Counler Overflow
Control Register
EDGE DETECT CAPABILITY
There Is an asynchronous edge detect capability on
two of the Port A 110 lines. This capability exists in ad-
dition to and Independently from the normal Port A
I/O functions. The maximum rate at whiCh an edge
can be detected Is one-half the 02 clock rate. The
edge detect logic Is contlriuously active. Each edge
detect signal Is associated with a maskable Interrupt.
PAO PosHIve Edge Detection
A positive (rising) edge Is detectable on .PAO. When
this edge Is detected, the PAO Positive Edge Detected
bit-Bit 61n the Control Register-Is set to Logic 1.
When both this bit and the PAO Interrupt Enable
Bit-Bit 3 of the Control Register-are sefto Logic 1,
an IRQ Interrupt request Is generated. The PAO
Positive Edge Detected bit Is cleared by writing to ad-
dress 089.
PA1 Negltlve Edge Detection
A negative (failing) edge is detectable on PAl.
When this edge Is detected, the PA1 Neg~tlve Edge
Detected bit-Bit 5 of the Control Register-Is set to
Logic 1. When both this bit and the PAl Interrupt
Enable bit-1m...2 of the Control Register-are set to
LogiC 1, an IRQ Interrupt request Is generated. The
PA1 Negative Edge Detected bit Is cleared by writing
to address OSA.
COUNTERILATCH
The Counter/Latch consists of a l6-blt decrement-
Ing Counter and a 16-blt Latch. The Counter Is com-
prised of two 8-bit registers. Address 086 contains the
Upper Count (UC) and address OS7 contains the Lower
Count (LC). The Counter counts either 02 clock
periods or occurrences of an external event, depend-
Ing on the selected counter mode. The UC and LC can
be read at any time without affecting counter opera-
tion.
The Latch contains the Counter preset value. The
Latch consists of two 6-blt registers. Address 084 con-
tains the Upper Latch (UL) and address 085 contains
the lower latch (LL). The 16-blt Latch can hold a count
from 0 to 65,535. The Latch can be accessed as two
wrlte-only memory locations.
The Latch registers can be loaded at any time by
storing Into UL and LL. The UL can also be loaded by
writing Into address 086.
The Counter can be preset at any time by writing to
address 086. Presetting the Counter In this manner
causes the contents of the accumulator to' be stored
Into the UL before the l6-blt value In the Latch (UL and
LL) Is transferred In the Counter (UC and LC).
The Counter Is preset to the Latch value when the
Counter overflows. When the counter decrements
from 0000, Counter overflow occurs causing the next
counter value to be the Latch value, not FFFF.
When the Counter overflOWS, Counter Overflow
bit-Bit 7 of the Control Register-Is set to Logic 1.
When both this bit and the Counter Interrupt Enable
bit-Bit 4 of the Control Register-are set, an Min-
terrupt request is generated. The Counter Overflow bit
In the Control Register can be examined In an IRQ in-
terrupt service routine to determine that the IRQ was
generated by Counter overflow.
2-4










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