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PDF MT18LSDT12872A Data sheet ( Hoja de datos )
| Número de pieza | MT18LSDT12872A | |
| Descripción | 1GB Synchronous DRAM Module | |
| Fabricantes | Micron | |
| Logotipo |  |
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512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
Features
Synchronous DRAM Module
MT9LSDT6472A - 512MB
MT18LSDT12872A - 1GB
For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/modules.
Features
• PC100- and PC133-compliant
• 168-pin, dual in-line memory module (DIMM)
• Unbuffered, ECC-optimized pinout
• 512MB (64 Meg x 72) and 1GB (128 Meg x 72)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto
precharge, and auto refresh modes
• Self refresh mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial presence-detect (SPD)
• Gold edge contacts
Table 1:
Timing Parameters
CL = CAS (READ) latency
Access Time
Module Clock
Setup
Marking Frequency CL = 2 CL = 3 Time
-13E
-133
133 MHz 5.4ns –
133 MHz – 5.4ns
1.5
1.5
Hold
Time
0.8
0.8
Figure 1: 168-Pin DIMM (MO-161)
Standard 1.375in./34.93mm
Low Profile 1.125in./28.58mm
Options
• Package
168-pin DIMM (standard)
168-pin DIMM (lead-free)
• Frequency/CAS latency
7.5ns (133 MHz)/CL = 2
7.5ns (133 MHz)/CL = 3
• PCB
Standard (1.375in./34.93mm)
Low-Profile (1.125in./28.58mm)
Marking
G
Y1
-13E
-133
See note 1 on
page 2
See note 1 on
page 2
Notes: 1. Contact Micron for product availability.
Table 2: Address Table
Parameter
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
512MB
8K
4 (BA0, BA1)
512Mb (64 Meg x 8)
8K (A0–A12)
2K (A0–A9, A11)
1 (S0#, S2#)
1GB
8K
4 (BA0, BA1)
512Mb (64 Meg x 8)
8K (A0–A12)
2K (A0–A9, A11)
2 (S0#, S2#; S1#, S3#)
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions (continued)
Pin numbers may not correlate with symbols; refer to the Table 4 on page 3 for pin number and symbol
information
Pin Numbers
82
Symbol
SDA
6, 18, 26, 40, 41, 49, 59, 73, 84,
90, 102, 110, 124, 133, 143,
157, 168
1, 12, 23, 32, 43, 54, 64, 68, 78,
85, 96, 107, 116, 127, 138, 148,
152, 162
24, 25, 31, 44, 48, 50, 51, 61,
62, 80, 81, 108, 109, 132, 134,
135, 145, 146, 147
VDD
VSS
NC
Type Descriptions
Input/ Serial presence-detect data: SDA is a bidirectional pin used to
Output transfer addresses and data into and out of the presence-
detect portion of the module.
Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
– Not Connected: These pins are not connected on these
modules.
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
5 Page 
512MB (SR), 1GB (DR): (x72, ECC) 168-Pin SDRAM UDIMM
Mode Register Definition
Table 6: Burst Definition Table
Burst
Length
2
4
8
Full Page
(y)
Starting Column Address
A0
0
1
A1 A0
00
01
10
11
A2 A1 A0
000
001
010
011
100
101
110
111
n = A0–A9, A11
(location 0-y)
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
0-1 0-1
1-0 1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn+1, Cn+2 Cn+3,
Cn+4...
...Cn-1,
Cn...
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
Notes: 1. For full-page accesses: y = 2,048.
2. For BL = 2, A1–A9, A11 select the block of two burst; A0 selects the starting column within
the block.
3. For BL = 4, A2–A9, A11 select the block of four burst; A0–A1 select the starting column
within the block.
4. For BL = 8, A3–A9, A11 select the block of eight burst; A0–A2 select the starting column
within the block.
5. For a full-page burst, the full row is selected and A0–A9, A11 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the follow-
ing access wraps within the block.
7. For BL = 1, A0–A9, A11 select the unique column to be accessed, and mode register bit M3
is ignored.
PDF: 09005aef8088b1bf/Source: 09005aef808807ca
SD9_18C64_128X72AG.fm - Rev. C 6/05 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
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