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PDF SM59264 Data sheet ( Hoja de datos )
| Número de pieza | SM59264 | |
| Descripción | 8-Bit Micro-controller | |
| Fabricantes | SyncMOS | |
| Logotipo |  |
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SyncMOS Technologies Inc.
SM59264
May 2002
Product List
Features
8 - Bit Micro-controller
with 128KB flash & 1KB RAM embedded
SM59264C25, 25 MHz 128KB internal flash MCU
SM59264C40, 40 MHz 128KB internal flash MCU
Description
The SM59264 series product is an 8 - bit single chip micro
controller with 128KB on-chip flash which including 64KB
program flash & 64KB data flash and 1K byte RAM
embedded. It has In-System Programming (ISP) function
and is a derivative of the 8052 micro controller family. It
has 4-channel SPWM build-in. User can access on-chip
expanded RAM with easier and faster way by its ‘bank
mapping direct addressing mode’ scheme. With its hard-
ware features and powerful instruction set, it’s straight for-
ward to make it a versatile and cost effective controller for
those applications which demand up to 32 I/O pins for
PDIP package or up to 36 I/O pins for PLCC/QFP pack-
age, or applications which need up to 64K byte flash mem-
ory for program and/or for data.
To program the on-chip flash memory, a commercial writer
is available to do it in parallel programming method. The
on-chip flash memory can be programmed in either paral-
lel or serial interface with its ISP feature.
Ordering Information
yywwv
SM59264ihhk
yy: year, ww:week
v: version identifier { , A, B, ...}
i: process identifier
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
Postfix
P
J
Q
Package
40L PDIP
44L PLCC
44L QFP
Pin/Pad
Configuration
page 2
page 2
page 2
Dimension
page 28
page 29
page 30
Working voltage:4.5V through 5.5V
General 8052 family compatible
12 clocks per machine cycle
64K byte on chip program flash with In-System
Programming (ISP) capability
64K byte on-chip data flash with ISP capability
1024 byte on-chip RAM
Three 16 bit Timers/Counters
One Watch Dog Timer
Four 8-bit I/O ports for PDIP package
Four 8-bit I/O ports + one 4-bit I/O ports for PLCC or QFP
package
Full duplex serial channel
Bit operation instruction
Industrial Level
8-bit Unsigned Division
8-bit Unsigned Multiply
BCD arithmetic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A serial I/O port
Power save modes: Idle mode and Power down mode
Code protection function
Low EMI (inhibit ALE)
Reset with address $0000 blank initiate ISP service program
ISP service program space configurable in N*512 byte
(N=0 to 8) size
Bank mapping direct addressing mode for access on-chip RAM
4 channel SPWM function
Web site: http://www.syncmos.com.tw
Specifications subject to change without notice,contact your sales representatives for the most recent information.
1/32
Taiwan
4F, No. 1 Creation Road 1,
Science-based Industrial Park,
Hsinchu, Taiwan 30077
TEL: 886-3-578-3344 #2667
886-3-579-2987
FAX: 886-3-5792960
886-3-5780493
Ver 1.2 SM59264 05/02
1 page  
SyncMOS Technologies Inc.
May 2002
SM59264
Special Function Register (SFR)
The address $80 to $FF can be accessed by direct addressing mode only.
Address $80 to $FF is SFR area.
The following table lists the SFRs which are identical to general 8052, as well as SM59264 Extension SFRs.
Special Function Register (SFR) Memory Map
$F8
$F0 B
ISPFAH ISPFAL ISPFD
ISPC
$E8
$E0 ACC
$D8 P4
$D0 PSW
$C8 T2CON
$C0
T2MOD
RCAP2L
RCAP2H
TL2
TH2
$B8 IP
$B0 P3
$A8 IE
$A0 P2
$98 SCON
$90 P1
$88 TCON
$80 P0
SBUF
TMOD
SP
SCONF
SPWMC SPWMD0 SPWMD1 SPWMD2 SPWMD3
P1CON
WDTC
WDTKEY
TL0 TL1 TH0 TH1
DPL
DPH
(Reserved) RCON DBANK
PCON
Note: The text of SFRs with bold type characters are Extension Special Function Registers forSM59264
$FF
$F7
$EF
$E7
$DF
$D7
$CF
$C7
$BF
$B7
$AF
$A7
$9F
$97
$8F
$87
Addr
85H
86H
97H
9BH
9FH
A3H
A4H
A5H
A6H
A7H
BFH
C8H
C9H
D8H
SFR
Reset
7
6
5
4
3 210
RCON
00H
RAMS7 RAMS6 RAMS5 RAMS4 RAMS3 RAMS2 RAMS1 RAMS0
DBANK 0***0001
BSE
BS3 BS2 BS1 BS0
WDTKEY 00H WDTKEY7 WDTKEY6 WDTKEY5 WDTKEY4 WDTKEY3 WDTKEY2 WDTKEY1 WDTKEY0
P1CON **0000**
SPWME3 SPWME2 SPWME1 SPWME0
WDTC 0*0**000 WDTE Reserve CLEAR
PS2 PS1 PS0
SPWMC ******00
SPFS1 SPFS0
SPWMD0 00H SPWMD04 SPWMD03 SPWMD02 SPWMD01 SPWMD00 BRM02 BRM01 BRM00
SPWMD1 00H SPWMD14 SPWMD13 SPWMD12 SPWMD11 SPWMD10 BRM12 BRM11 BRM10
SPWMD2 00H SPWMD24 SPWMD23 SPWMD22 SPWMD21 SPWMD20 BRM22 BRM21 BRM20
SPWMD3 00H SPWMD34 SPWMD33 SPWMD32 SPWMD31 SPWMD30 BRM32 BRM31 BRM30
SCONF 0***_0000 WDR
DFEN
ISPE
OME
ALEI
T2CON
00H
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2 CP/RL2
T2MOD ******00
*
*
*
*
*
*
T2OE
DCEN
P4 ****1111
P4.3
P4.2
P4.1
P4.0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
5/32 Ver 1.2 SM59264 05/02
5 Page 
SyncMOS Technologies Inc.
May 2002
SM59264
One page of data RAM is 256 bytes.
The port 0, port2, port3.6 and port3.7 can be used as general purpose I/O pin while port0 is open-drain structure.
System Control Register (SCONF, $BF)
Read / Write:
Reset value:
bit-7
WDR
R/W
0
Unused
-
*
Unused
-
*
Unused
-
*
DFEN
R/W
0
ISPE
R/W
0
OME
R/W
0
bit-0
ALEI
R/W
0
WDR: Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1, The bit
7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT
overflow. User should check WDR bit whenever un-predicted reset happened.
DFEN: 64K Data Flash enable bit. The default setting of DFEN bit is 0 (disable).
ISPE: ISP enable bit
OME: 768 bytes on-chip RAM enable bit, The bit 1 (OME) of SCONF can enable or disable the on-chip expanded
768 byte RAM. The default setting of OME bit is 0 (disable).
ALEI: ALE output inhibit bit, to reduce EMI, Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz
output to the ALE pin.
1.5 I/O Pin Configuration
The ports 1, 2 and 3 of standard 8051 have internal pull-up resistor, and port 0 has open-drain outputs. Each I/O pin can
be used independently as an input or an output. For I/O ports to be used as an input pin, the port bit latch must contain a
‘1’ which turns off the output driver FET. Then for port 1, 2 and 3 port pin is pulled high by a weak internal pull-up, and can
be pulled low by an external source. The port 0 has open-drain outputs which means its pull-ups are not active during nor-
mal port operation. Writing ‘1’ to the port 0 bit latch will causing bit floating so that it can be used as a high-impedance
input.
The port 4 used as GPIO will has the same function as port 1, 2 and 3.
output
data
input
data
port 0
pin standard 8051
output
data
input
data
port 1, 2 and 3
standard 8051
pin
Specifications subject to change without notice,contact your sales representatives for the most recent information.
11/32
Ver 1.2 SM59264 05/02
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SM59264.PDF ] | |
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