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Номер произв M5M4257L-20
Описание 256K-Bit DRAM
Производители Mitsubishi
логотип Mitsubishi логотип 



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M5M4257L-20 Даташит, Описание, Даташиты
MITSUBISHI LSls
M5M4257L.12, ·15, ·20
262 144-BIT (262 144-WORD BY I-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 262 144-word by 1-bit dynamic RAMs,
fabricated with the high performance N-channel silicon gate
MOS process, and is ideal for large-capacity memory
systems where high speed, low power dissipation, and low
costs are essential. The use of double-layer polysilicon
process combined with silicide technology and a single-
transistor dynamic storage cell provide high circuit density
at reduced costs, and the use of dynamic circuitry including
sense amplifiers assures low power dissipation_ Multiplexed
address inputs permit both a reduction in pins to the 16 pin
zigzag inline package configuration and an increase in
system densities_ In addition to the RAS only refresh mode,
the Hidden refresh mode and CAS before RAS refresh
mode are available_
FEATURES
Type name
Access time
(max)
(ns)
Cycle tIme
(min)
(ns)
Power diSSipation
(typ)
(mW)
M5M4257L-12
120
230
260
M5M4257L-15
150
260
230
M5M4257L-20
200
330
190
• 16 pm zigzag mime package
• Single 5V±10% supply
• Low standby power dissipation:
25mW (max)
• Low operating power dissipation:
M5M4257L-12- - - - - ...... 360mW (max)
M5M4257L-15- .......... 330mW (max)
M5M4257 L-20 .... _ .. _... 275mW (max)
• Unlatched output enables two-dimensional chip selec-
tion
BLOCK DIAGRAM
PIN CONFIGURATION (TOP VIEW)
ADDRESS INPUT
As
i]
CDLUMN ADDRESS
STRDBE INPUT
CAS
i]
[~
[~
Q DATA DUTPUT
Vss (OV)
ADDRESS INPUT
WRITE CDNTRDL
INPUT
'"""" { .''r".".INPUTS
As
W
~J
fJ
~
~
[~
[~
+-D DATA INPUT
RAS ~~:D:~~~pE~i
Ao ~J
<.n i,-O +- A2 ADDRESS INPUT
A, -+ (lJ
L_
~j Vee (5V)
A7 -. 1)]
A4 -+ (5J
J:4 +- As } ADDRESS
[(6 +- A3 INPUTS
Outline 16P5A
• Early-write operation gives common I/O capability
• Read-modify-write, RAS-only-refresh, Nibble-mode
capabilities. (Pin 1 is used for nibble mode)
• CAS before RAS refresh mode capability
• All input terminals have low input capacitance and are
directly TTL-compatible
• Output is three-state and directly TTL-compatible
• 256 refresh cycles every 4ms. Pin 1 is not needed for
refresh.
• CAS controlled output allows hidden refresh
APPLICATION
• Main memory unit for computers
• Microcomputer memory
DATA INPUT
WRITE CDNTRDL
INPUT
D 6 ~------------------------------------------------,
W 7 ~----------------------------<I
INPUT
LATCH
ADDRESS
INPUTS
A,
A2
A3
A4
As
A7
32K
MEMDRY
ARRAY
a:
w
0
u0
w
0
32K
MEMDRY
ARRAY
32K
MEMDRY
ARRAY
cr:
w
0
0
::d
0
32K
MEMDRY
ARRAY
CDLUMN
DECDDER
32K
MEMDRY
ARRAY
~
0
a:
32K
MEMDRY
ARRAY
32K
MEMDRY
ARRAY
~
0
cr:
32K
MEMDRY
ARRAY
wcc
0
0uw
0
:':j
ccoo
Z
l-
Succ
U
..J
0
0:
Iz-
0u
~
I
~veC(5V)
,
1'%'"
DATA
DUTPUT
• MITSUBISHI
~ELECTRIC
2-155









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M5M4257L-20 Даташит, Описание, Даташиты
MITSUBISHI LS1s
MSM42S7L-12, -15, -20
262 144-BIT (262 144-WORD BY I-BIT) DYNAMIC RAM
FUNCTION
The M5M4257L provides, in addition to normal read,
write, and read-modify-write operations, a number of other
functions, e.g., nibble mode, RAS-only refresh, and delayed-
write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
RAS CAS
Inputs
Iii 0
Row
Column
address address
Read ACT ACT NAC DNC APD APD
Write
ACT ACT ACT VLD APD APD
Read-modify-write
ACT ACT ACT VLD APD APD
AAS-only refresh
ACT NAC DNC DNC APD DNC
Hidden refresh
ACT ACT DNC DNC DNC DNC
CAS before RAS refresh
ACT ACT DNC DNC DNC DNC
Standby
NAC DNC DNC DNC DNC DNC
*Note: ACT: active, NAC: nonactive, ONe: don t care, VLO. valid, APO. applied, OPN. open.
~
'Nibble mode identical except refresh is No, and Nibble mode column address is ONe while togging CAS
Output
Q
VLD
OPN
VLD
OPN
VLD
OPN
OPN
Refresh
YES
YES
YES
YES
YES
YES
NO
Remarks
*
SUMMARY OF OPERATIONS
Addressing
To select one of the 262144 memory cells in the
M5M4257L the 18-bit address signal must be multiplexed
into 9 address signals, which are then latched into the
on-chip latch by two externally·applied clock pulses. First,
the negative-going edge of the row-address-strobe, pulse
(RAS) latches the 9 row-address bits; next, the negative-
going edge of the column-address-strobe pulse (CAS)
latches the 9 column-address bits. Timing of the RAS and
CAS clocks can be selected by either of the following two
methods:
1. The delay time from RAS to CAS td (RAS-CAS) is set
between the minimum and maximum values of the
limits. In this case, the internal CAS control signals are
inhibited almost until td(RAS-CAS) max ('gated CAS'
operation). The external CAS signal can be applied with
a margin not affecting the on-chip circuit operations, e.g.
access time, and the address inputs can be easily changed
from row address to column address.
2. The delay time td(RAS.CAS) is set larger, than the
maximum value of the limits. In this case the internal
inhibition of CAS has already been released, so that the
internal CAS control signals are controlled by the
externally applied CAS, which also controls the access
time.
Data Input
Data to be written into a selected cell is strobed by the later
of the two negative transitions of W input and CAS input.
Thus when the IN input makes its negative transition prior
to CAS input (early write). the data input is strobed by
CAS, and the negative transition of CAS is set as the
reference point for set-up and hold times. In the read-write
or read-modify-write cycles,however, when the IN input
makes its negative transition after CAS, the IN negative
transition is set as the reference point for setup and hold
times.
Data Output Control
The output of the M5M4257L IS In the high-impedance
state when CAS is high. When the memory cycle in progress
is a read, read-modify-write, or a delayed-write cycle, the
data output will go from the high-impedance state to the
active condition, and the data in the selected cell will be
read. This data output will have the same polarity as the
input data. Once the output has entered the active
condition, this condition will be maintained until CAS goes
high, irrespective of the condition of RAS.
The output will remain in the high-impedance state
throughout the entire cycle in an early-write cycle.
These output conditions, of the M5M4257L, which can
readily be' changed by controlling the timing of the write
pulse in a write cycle, and the width of the CAS pulse in a
read cycle, offer capabilities for a number of applications,
as follows.
1. Common I/O Operation
If all write operations are performed in the early-write
mode, input and output can be connected directly to give a
common I/O data bus.
2 Data Output Hold
The data output can be held between read cycles, without
lengthening the cycle time. This enables extremely flexible
clock-timing settings for RAS and CAS.
2-156
• MITSUBISHI
...... ELECTRIC









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M5M4257L-20 Даташит, Описание, Даташиты
MITSUBISHI LSls
M5M4257L-12, -15, -20
262 144·BIT (262 144·WORD BY I.BIT) DYNAMIC RAM
3. Two Methods of Chip Selection
Since the output is not latched, CAS is not required to keep
the outputs of selected chips in the matrix in a high-
impedance state. This means that CAS and/or RAS can
both be decoded for chip selection_
4. Extended·Page Boundary
By decoding CAS, the page boundary can be extended
beyond the 512 column locations in a single chip. In this
case, RAS must be applied to all devices.
Nibble-Mode Operation
The M5M4257L is designed to allow high speed serial read,
write or read-modify-write access of 4 bits of data. The
first of 4 nibble bits is accessed by the normal mode with
read data coming out at ta(CAS) time. Next 2, 3 or 4 nibble
bits is read or writen by bringing CAS high then low
(toggle) while RAS remains low. Thus the time required to
strobe in not only the row address but also the column
address is eliminated, thereby faster access and shorter
cycle time than that of Page-Mode is achieved.
Address on pin 1 (row address AS and column address
AS) is used to select 1 of the 4 nibble bits for initial access.
Toggling CAS causes row AS and column AS to be in-
cremented by the internal shift register with AS row being
the least significant address and allows to access to the next
nibble bit. If more than 4 bits are accessed during this mode
the same address bit will be accessed cyclically. In Nibble-
Mode, any combination of read, write and read-modify-
write operation is possible (e_g_ first bit read, second bit
write, third bit read-modify-write, etc.)_
Refresh
Each of the 256 rows (Ao - A7) of the M5M4257 L must
be refreshed every 4 ms to maintain data. The methods of
refreshing for the M5M4257 L are as follows.
1. Normal Refresh
Read cycle and Write cycle (early write, delayed write or
read-modify-write) refresh the selected row as defined by
the low order (RAS) addresses. Any write cycle, of course,
may change the state of the selected cell. Using a read,
write, or read-modify-write cycle for refresh is not recom-
mended for systems which utilize "wired-OR" outputs
since output bus contention will occur.
2. RAS Only Refresh
In this refresh method, the CAS clock should be at a
V1H level and the system must perform RAS Only cycle on
all 256 row address every 4 ms. The sequential row ad-
dresses from an external counter are latched with the RAS
clock and associated internal row locations are refreshed. A
RAS Only Refresh cycle maintains the output in the high
impedance state with a typical power reduction of 20%
over a read or write cycle.
3. CAS before RAS Refresh
If CAS falls tSUR(CAS-RAS) earlier than RAS and if CAS
is kept low by thR (RAS-CAS) after RAS falls, CAS before
RAS Refresh is initiated. The external address is ignored
and the refresh address generated by the internal S-bit
counter is put into the address buffer to refresh the cor-
responding row. The output will stay in the high impedance
state.
If CAS is kept low after the above operation, RAS cycle
initiates RAS Only Refresh with internally generated re-
fresh address (Automatic refresh)' The output will again
stay in the high impedance state.
Bringing RAS high and then low while CAS remains high
initiates the normal RAS Only Refresh using the external
address.
If CAS is kept low after the normal read/write cycle,
RAS cycle initiates the RAS Only Refresh using the inter-
nal refresh address and especially after the normal read
cycle, it becomes Hidden Refresh with internal address.
The output is available unit CAS is brought high.
4. Hidden Refresh
A feature of the M5M4257 L is that refresh cycles may
be performed while maintaining valid data at the output pin
by extending the CAS active time from a previous memory
read cycle. This feature is referred to as hidden refresh.
Hidden refresh is performed by holding CAS at V I Land
taking RAS high and after a specified precharge period,
executing a RAS'only cycling, but with CAS held low.
The advantage of this refresh mode is that data can be
held valid at the output data port indefinitely by leaving
the CAS asserted. In many applications this eliminates the
need for off-chip latches.
Power Dissipation
Most of the circuitry in the M5M4257L is dynamic, and
most of the power is dissipated when addresses are strobed.
Both RAS and CAS are decoded and applied to the
M5M4257L as Chip-select in the memory system, but if
RAS is decoded, all unselected devices go into stand-by
independent of the CAS condition, minimizing system
power dissipation.
Power Supplies
The M5M4257L operates on a single 5V power supply.
A wait of some 500).ls and eight or more dummy cycles
is necessary after power is applied to the device before
memory operation is achieved.
• MITSUBISHI
...... ELECTRIC
2-157










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