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PDF ST7260E1 Data sheet ( Hoja de datos )
| Número de pieza | ST7260E1 | |
| Descripción | Low speed USB 8-bit MCU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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ST7260xx
Low speed USB 8-bit MCU family with up to 8K Flash
and serial communications interface
Features
■ Memories
– 4 or 8 Kbytes program memory: high
density Flash (HDFlash), or FastROM with
readout and write protection
– In-application programming (IAP) and in-
circuit programming (ICP)
– 384 bytes RAM memory (128-byte stack)
■ Clock, reset and supply management
– Run, Wait, Slow and Halt CPU modes
– 12 or 24 MHz oscillator
– RAM Retention mode
– Optional low voltage detector (LVD)
■ USB (Universal Serial Bus) interface
– DMA for low speed applications compliant
with USB 1.5 Mbs (version 2.0) and HID
specifications (version 1.0)
– Integrated 3.3 V voltage regulator and
transceivers
– Supports USB DFU class specification
– Suspend and Resume operations
– 3 Endpoints with programmable In/Out
configuration
■ Up to 19 I/O ports
– Up to 8 high sink I/Os (10 mA at 1.3 V)
Table 1. Device summary
SO24
QFN40
(6x6)
– 2 very high sink true open drain I/Os (25
mA at 1.5 V)
– Up to 8 lines with interrupt capability
■ 2 timers
– Programmable Watchdog
– 16-bit Timer with 2 Input Captures, 2
Output Compares, PWM output and clock
input
■ Communications interface
– Asynchronous serial communications
interface (SCI)
■ Instruction set
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
■ Development tools
– Versatile development tools including ,
software library, hardware emulator,
programming boards, HID and DFU
software layer
Features
ST7260K2
ST7260K1
ST7260E2
ST7260E1
Flash program memory -
bytes
RAM (stack) - bytes
Peripherals
Operating supply
CPU frequency
Operating temperature
Packages
8K 4K 8K 4K
384 (128)
Watchdog timer, 16-bit timer, USB, SCI
4.0 V to 5.5 V
8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)
0 °C to +70 °C
QFN40 (6x6)
SO24
February 2009
Rev 3
1/139
www.st.com
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1 page  
ST7260xx
Contents
14.5
14.4.9 Endpoint n register B (EPnRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.4.10 Endpoint 0 register B (EP0RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.5.1 Initializing the registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.5.2 Initializing DMA buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14.5.3 Endpoint initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
14.5.4 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
15 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
15.1 ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
15.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
15.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
15.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
15.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
15.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
15.1.6 Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
15.1.7 Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
15.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
16 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
16.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
16.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
16.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
16.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 113
16.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
16.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
16.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
16.5.2 Control timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
16.5.3 External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
16.6 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5/139
5 Page 
ST7260xx
Pin description
Table 2.
Pin n°
)
Device pin description (QFN40)
Level
Pin name
Port / control
Input
Output
Main
function
(after
reset)
Alternate function
1 PA0/MCO
2 VSSA
3 USBDP
4 USBDM
5 USBVCC
6 VDDA
7 VDD
8 OSCOUT
9 OSCIN
10 VSS
11 PC2/USBOE
12 PC1/TDO
13 PC0/RDI
14 RESET
15 NC
16 NC
17 PB7/IT8
18 PB6/IT7
19 VPP/TEST
20 PB5/IT6
21 PB4/IT5
22 PB3
23 PB2
24 PB1
25 PB0
26 PA7/OCMP2/IT4
27 PA6/OCMP1/IT3
28 PA5/ICAP2/IT2
29 PA4/ICAP1/IT1
I/O CT
X X Port A0 Main Clock Output
S Analog ground
I/O USB bidirectional data (data +)
I/O USB bidirectional data (data -)
O USB power supply
S Analog supply voltage
S Power supply voltage (4V - 5.5V)
O Oscillator output
I Oscillator input
S Digital ground
I/O CT
X
X Port C2 USB Output Enable
I/O CT
X
X Port C1
SCI Transmit Data
Output
I/O CT
X
X Port C0
SCI Receive Data
Input
I/O X X Reset
-- Not connected
-- Not connected
I/O CT 10 mA X X X Port B7
I/O CT 10 mA X X X Port B6
S Programming supply
I/O CT 10 mA X X X Port B5
I/O CT 10 mA X X X Port B4
I/O CT 10 mA X
X Port B3
I/O CT 10 mA X
X Port B2
I/O CT 10 mA X
X Port B1
I/O CT 10 mA X
X Port B0
I/O CT
XX
X Port A7
Timer Output Compare
2
I/O CT
XX
X Port A6
Timer Output Compare
1
I/O CT
XX
X Port A5 Timer Input Capture 2
I/O CT
XX
X Port A4 Timer Input Capture 1
11/139
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ST7260E1.PDF ] | |
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