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PDF MK30DN512ZVLQ10 Data sheet ( Hoja de datos )
| Número de pieza | MK30DN512ZVLQ10 | |
| Descripción | K30 MCU | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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K30 Sub-Family Reference Manual
Supports: MK30DX128ZVLQ10, MK30DX128ZVMD10,
MK30DX256ZVLQ10, MK30DX256ZVMD10, MK30DN512ZVLQ10,
MK30DN512ZVMD10
Document Number: K30P144M100SF2RM
Rev. 6, Nov 2011
1 page  
Section Number
Title
Page
3.5.5 System Register File Configuration.............................................................................................................104
3.5.6 VBAT Register File Configuration..............................................................................................................105
3.5.7 EzPort Configuration...................................................................................................................................106
3.5.8 FlexBus Configuration.................................................................................................................................107
3.6 Security.........................................................................................................................................................................110
3.6.1 CRC Configuration......................................................................................................................................110
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
5
5 Page 
Section Number
Title
Page
11.4.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................255
11.4.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................255
11.5 Functional description...................................................................................................................................................256
11.5.1 Pin control....................................................................................................................................................256
11.5.2 Global pin control........................................................................................................................................256
11.5.3 External interrupts........................................................................................................................................257
11.5.4 Digital filter..................................................................................................................................................258
Chapter 12
System integration module (SIM)
12.1 Introduction...................................................................................................................................................................259
12.1.1 Features........................................................................................................................................................259
12.1.2 Modes of operation......................................................................................................................................259
12.1.3 SIM Signal Descriptions..............................................................................................................................260
12.2 Memory map and register definition.............................................................................................................................260
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................262
12.2.2 System Options Register 2 (SIM_SOPT2)..................................................................................................264
12.2.3 System Options Register 4 (SIM_SOPT4)..................................................................................................266
12.2.4 System Options Register 5 (SIM_SOPT5)..................................................................................................269
12.2.5 System Options Register 6 (SIM_SOPT6)..................................................................................................270
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................271
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................273
12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................274
12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2)............................................................................275
12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)............................................................................276
12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................277
12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................280
12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................282
12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................284
12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................285
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MK30DN512ZVLQ10.PDF ] | |
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