CY8C3245 PDF даташит
Спецификация CY8C3245 изготовлена «Cypress Semiconductor» и имеет функцию, называемую «Programmable System-on-Chip». |
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Детали детали
Номер произв | CY8C3245 |
Описание | Programmable System-on-Chip |
Производители | Cypress Semiconductor |
логотип |
30 Pages
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PSoC® 3: CY8C32 Family
Data Sheet
Programmable System-on-Chip (PSoC®)
General Description
With its unique array of configurable blocks, PSoC® 3 is a true ystem level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C32 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C32 family can handle dozens of data acquisition channels and analog inputs on
every general-purpose input/output (GPIO) pin. The CY8C32 family is also a high-performance configurable digital system with some
part numbers including interfaces such as USB, and multimaster inter-integrated circuit (I2C). In addition to communication interfaces,
the CY8C32 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance single cycle 8051
microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives
using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C32 family provides unparalleled opportunities for analog
and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.
Features
Single cycle 8051 CPU core
Full-speed (FS) USB 2.0 12 Mbps using internal oscillator[2]
DC to 50 MHz operation
Up to four 16-bit configurable timer, counter, and PWM blocks
Multiply and divide instructions
Flash program memory, up to 64 KB, 100,000 write cycles,
20 years retention, and multiple security features
Up to 8-KB flash error correcting code (ECC) or configuration
storage
Up to 8 KB SRAM
Up to 2 KB electrically erasable programmable read-only
memory (EEPROM), 1 M cycles, and 20 years retention
2A4H-Bch[1a] nbnuesl
direct memory
access
access
(DMA)
with
multilayer
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Low voltage, ultra low-power
Wide operating voltage range: 0.5 V to 5.5 V
High efficiency boost regulator from 0.5-V through 1.8-V to
5.0-V output
0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 50 MHz
Low-power modes including:
• 1-µA sleep mode with real-time clock (RTC) and
low-voltage detect (LVD) interrupt
Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• Serial peripheral interface (SPI), universal asynchronous
transmitter receiver (UART), and I2C
• Many others available in catalog
Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
1.024 V ±0.9-percent internal voltage reference across –40°C
to +85°C (14 ppm/°C)
Configurable delta-sigma ADC with 8- to12-bit resolution
• Programmable gain stage: ×0.25 to ×16
• 12-bit mode, 192-ksps, 66-dB signal to noise and distortion
ratio (SINAD), ±1-bit INL/DNL
One 8-bit, 8-Msps IDAC or 1-Msps VDAC
Two comparators with 95 ns response time
CapSense support
• 200-nA hibernate mode with RAM retention
Programming, debug, and trace
Versatile I/O system
28 to 72 I/O (62
two USBIOs[2])
GPIOs,
eight
special
input/outputs
(SIO),
JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
wire viewer (SWV) interfaces
Eight address and one data breakpoint
Any GPIO to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46×16 segments[2]
CapSense® support from any GPIO[3]
1.2-V to 5.5-V I/O interface voltages, up to four domains
Maskable, independent IRQ on any pin or port
Schmitt-trigger transistor-transistor logic (TTL) inputs
All GPIO configurable as open drain high/low,
pull-up/pull-down, High Z, or strong output
Configurable GPIO pin state at power-on reset (POR)
25 mA sink on SIO
Digital peripherals
16 to 24 programmable PLD based universal digital
blocks (UDB)
4-KB instruction trace buffer
Bootloader programming supportable through I2C, SPI,
UART, USB, and other interfaces
Precision, programmable clocking
3- to 24-MHz internal oscillator over full temperature and
voltage range
4- to 25-MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 50 MHz
32.768-kHz watch crystal oscillator
Low-power internal oscillator at 1, 33, and 100 kHz
Temperature and packaging
–40°C to +85°C degrees industrial temperature
48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP
package options
Notes
1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
2. This feature on select devices only. See Ordering Information on page 108 for details.
3. GPIOs with opamp outputs are not recommended for use with CapSense.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-56955 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 20, 2011
No Preview Available ! |
PSoC® 3: CY8C32 Family
Data Sheet
Contents
1. Architectural Overview ..................................................... 3
2. Pinouts ............................................................................... 5
3. Pin Descriptions .............................................................. 10
4. CPU ................................................................................... 11
4.1 8051 CPU ................................................................. 11
4.2 Addressing Modes .................................................... 11
4.3 Instruction Set .......................................................... 12
4.4 DMA and PHUB ....................................................... 16
4.5 Interrupt Controller ................................................... 18
5. Memory ............................................................................. 22
5.1 Static RAM ............................................................... 22
5.2 Flash Program Memory ............................................ 22
5.3 Flash Security ........................................................... 22
5.4 EEPROM .................................................................. 22
5.5 Nonvolatile Latches (NVLs) ...................................... 23
5.6 External Memory Interface ....................................... 24
5.7 Memory Map ............................................................ 24
6. System Integration .......................................................... 26
6.1 Clocking System ....................................................... 26
6.2 Power System .......................................................... 29
6.3 Reset ........................................................................ 33
6.4 I/O System and Routing ........................................... 34
7. Digital Subsystem ........................................................... 40
7.1 Example Peripherals ................................................ 41
7.2 Universal Digital Block .............................................. 44
7.3 UDB Array Description ............................................. 47
7.4 DSI Routing Interface Description ............................ 47
7.5 USB .......................................................................... 49
7.6 Timers, Counters, and PWMs .................................. 49
7.7 I2C ............................................................................ 49
8. Analog Subsystem .......................................................... 51
8.1 Analog Routing ......................................................... 52
8.2 Delta-sigma ADC ...................................................... 54
8.3 Comparators ............................................................. 55
8.4 LCD Direct Drive ...................................................... 57
8.5 CapSense ................................................................. 57
8.6 Temp Sensor ............................................................ 57
8.7 DAC .......................................................................... 58
9. Programming, Debug Interfaces, Resources ................ 59
9.1 JTAG Interface ......................................................... 59
9.2 Serial Wire Debug Interface ..................................... 61
9.3 Debug Features ........................................................ 62
9.4 Trace Features ......................................................... 62
9.5 Single Wire Viewer Interface .................................... 62
9.6 Programming Features ............................................. 62
9.7 Device Security ........................................................ 62
10. Development Support ................................................... 63
10.1 Documentation ....................................................... 63
10.2 Online ..................................................................... 63
10.3 Tools ....................................................................... 63
11. Electrical Specifications ............................................... 64
11.1 Absolute Maximum Ratings .................................... 64
11.2 Device Level Specifications .................................... 65
11.3 Power Regulators ................................................... 69
11.1 Inputs and Outputs ................................................. 73
11.2 Analog Peripherals ................................................. 81
11.3 Digital Peripherals .................................................. 93
11.4 Memory .................................................................. 96
11.5 PSoC System Resources ..................................... 102
11.6 Clocking ................................................................ 104
12. Ordering Information ................................................... 108
12.1 Part Numbering Conventions ............................... 109
13. Packaging ..................................................................... 110
14. Acronyms ..................................................................... 113
15. Reference Documents ................................................. 114
16. Document Conventions .............................................. 115
16.1 Units of Measure .................................................. 115
17. Revision History .......................................................... 116
18. Sales, Solutions, and Legal Information .................120
Document Number: 001-56955 Rev. *K
Page 2 of 120
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PSoC® 3: CY8C32 Family
Data Sheet
1. Architectural Overview
Introducing the CY8C32 family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C32 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
4- 33 MHz
( Optional)
32.768 KHz
( Optional)
System Wide
Resources
Xtal
Osc
IMO
RTC
Timer
WDT
and
Wake
ILO
Clocking System
Power Management
System
POR and
LVD
Sleep
Power
1.8V LDO
SMP
Digital Interconnect
Analog Interconnect
Digital System
Universal Digital Block Array ( 24x UDB)
8- Bit Quadrature Decoder
Timer
16- Bit 16- Bit PRS
PWM
UDB
UDB
UDB
UDB
UDB
UDB
UDB
I2C Slave
UDB
UDB
UART
UDB
8- Bit SPI
UDB
UDB
UDB
12- Bit SPI
UDB
UDB
8- Bit
Timer Logic
UDB
Logic
UDB
12- Bit PWM
UDB
UDB
UDB
UDB
UDB
UDB
UDB
4x
Timer
Counter
PWM
I2C
Master/
Slave
FS USB
2.0
System Bus
Memory System
EEPROM
SRAM
CPU System
8051 or
Cortex M3
CPU
Interrupt
Controller
EMIF
FLASH
PHUB
DMA
Program &
Debug
Program
Debug &
Trace
Boundary
Scan
LCD Direct
Drive
Analog System
ADC
Temperature
Sensor
CapSense
DAC
Del Sig
ADC
+
2x
CMP
-
USB
PHY
22 Ω
0. 5 to5.5V
( Optional)
Figure 1-1 illustrates the major components of the CY8C32
family. They are:
8051 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
Document Number: 001-56955 Rev. *K
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the Digital System Interconnect (DSI). It also
provides functional flexibility through an array of small, fast,
low-power UDBs. PSoC Creator provides a library of prebuilt and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. You can also easily create a digital circuit using
boolean primitives by means of graphical design entry. Each
UDB contains programmable array logic (PAL)/programmable
logic device (PLD) functionality, together with a small state
machine engine to support a wide variety of peripherals.
Page 3 of 120
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Номер в каталоге | Описание | Производители |
CY8C3244 | Programmable System-on-Chip | Cypress Semiconductor |
CY8C3245 | Programmable System-on-Chip | Cypress Semiconductor |
CY8C3246 | Programmable System-on-Chip | Cypress Semiconductor |
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