|
|
PDF CY8C3244 Data sheet ( Hoja de datos )
| Número de pieza | CY8C3244 | |
| Descripción | Programmable System-on-Chip | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY8C3244 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
PSoC® 3: CY8C32 Family
Data Sheet
Programmable System-on-Chip (PSoC®)
General Description
With its unique array of configurable blocks, PSoC® 3 is a true ystem level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C32 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C32 family can handle dozens of data acquisition channels and analog inputs on
every general-purpose input/output (GPIO) pin. The CY8C32 family is also a high-performance configurable digital system with some
part numbers including interfaces such as USB, and multimaster inter-integrated circuit (I2C). In addition to communication interfaces,
the CY8C32 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance single cycle 8051
microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives
using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C32 family provides unparalleled opportunities for analog
and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.
Features
Single cycle 8051 CPU core
Full-speed (FS) USB 2.0 12 Mbps using internal oscillator[2]
DC to 50 MHz operation
Up to four 16-bit configurable timer, counter, and PWM blocks
Multiply and divide instructions
Flash program memory, up to 64 KB, 100,000 write cycles,
20 years retention, and multiple security features
Up to 8-KB flash error correcting code (ECC) or configuration
storage
Up to 8 KB SRAM
Up to 2 KB electrically erasable programmable read-only
memory (EEPROM), 1 M cycles, and 20 years retention
2A4H-Bch[1a] nbnuesl
direct memory
access
access
(DMA)
with
multilayer
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Low voltage, ultra low-power
Wide operating voltage range: 0.5 V to 5.5 V
High efficiency boost regulator from 0.5-V through 1.8-V to
5.0-V output
0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 50 MHz
Low-power modes including:
• 1-µA sleep mode with real-time clock (RTC) and
low-voltage detect (LVD) interrupt
Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• Serial peripheral interface (SPI), universal asynchronous
transmitter receiver (UART), and I2C
• Many others available in catalog
Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
1.024 V ±0.9-percent internal voltage reference across –40°C
to +85°C (14 ppm/°C)
Configurable delta-sigma ADC with 8- to12-bit resolution
• Programmable gain stage: ×0.25 to ×16
• 12-bit mode, 192-ksps, 66-dB signal to noise and distortion
ratio (SINAD), ±1-bit INL/DNL
One 8-bit, 8-Msps IDAC or 1-Msps VDAC
Two comparators with 95 ns response time
CapSense support
• 200-nA hibernate mode with RAM retention
Programming, debug, and trace
Versatile I/O system
28 to 72 I/O (62
two USBIOs[2])
GPIOs,
eight
special
input/outputs
(SIO),
JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
wire viewer (SWV) interfaces
Eight address and one data breakpoint
Any GPIO to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46×16 segments[2]
CapSense® support from any GPIO[3]
1.2-V to 5.5-V I/O interface voltages, up to four domains
Maskable, independent IRQ on any pin or port
Schmitt-trigger transistor-transistor logic (TTL) inputs
All GPIO configurable as open drain high/low,
pull-up/pull-down, High Z, or strong output
Configurable GPIO pin state at power-on reset (POR)
25 mA sink on SIO
Digital peripherals
16 to 24 programmable PLD based universal digital
blocks (UDB)
4-KB instruction trace buffer
Bootloader programming supportable through I2C, SPI,
UART, USB, and other interfaces
Precision, programmable clocking
3- to 24-MHz internal oscillator over full temperature and
voltage range
4- to 25-MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 50 MHz
32.768-kHz watch crystal oscillator
Low-power internal oscillator at 1, 33, and 100 kHz
Temperature and packaging
–40°C to +85°C degrees industrial temperature
48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP
package options
Notes
1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
2. This feature on select devices only. See Ordering Information on page 108 for details.
3. GPIOs with opamp outputs are not recommended for use with CapSense.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-56955 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 20, 2011
1 page  
PSoC® 3: CY8C32 Family
Data Sheet
This enables the device to be powered directly from a single
battery or solar cell. In addition, you can use the boost converter
to generate other voltages required by the device, such as a
3.3-V supply for LCD glass drive. The boost’s output is available
on the VBOOST pin, allowing other devices in the application to
be powered from the PSoC.
PSoC supports a wide range of low-power modes. These include
a 200-nA hibernate mode with RAM retention and a 1-µA sleep
mode with RTC. In the second mode the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 1.2 mA when the CPU is running at
6 MHz, or 0.8 mA running at 3 MHz.
The details of the PSoC power modes are covered in the “Power
System” section on page 29 of this datasheet.
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. The 1-wire SWV may also be
used for “printf” style debugging. By combining SWD and SWV,
you can implement a full debugging interface with just three pins.
Using these standard interfaces enables you to debug or
program the PSoC with a variety of hardware solutions from
Cypress or third party vendors. PSoC supports on-chip break
points and 4-KB instruction and data race memory for debug.
Details of the programming, test, and debugging interfaces are
discussed in the “Programming, Debug Interfaces, Resources”
section on page 59 of this datasheet.
2. Pinouts
The Vddio pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in Figure 2-1
through Figure 2-4. Using the Vddio pins, a single PSoC can
support multiple interface voltage levels, eliminating the need for
off-chip level shifters. Each Vddio may sink up to 100 mA total to
its associated I/O pins. On the 68 pin and 100 pin devices each
set of Vddio associated pins may sink up to 100 mA. The 48-pin
device may sink up to 100 mA total for all Vddio0 plus Vddio2
associated I/O pins and 100 mA total for all Vddio1 plus Vddio3
associated I/O pins.
Figure 2-1. 48-pin SSOP Part Pinout
(SIO) P12[2]
(SIO) P12[3]
(GPIO) P0[0]
(GPIO) P0[1]
(GPIO) P0[2]
(Extref0, GPIO) P0[3]
Vddio0
(GPIO) P0[4]
(GPIO) P0[5]
(IDAC0, GPIO) P0[6]
(GPIO) P0[7]
Vccd
Vssd
Vddd
(GPIO) P2[3]
(GPIO) P2[4]
Vddio2
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
Vssb
Ind
Vboost
Vbat
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Lines show
Vddio to I/O
supply
association
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
Vddio3
P15[1] (GPIO, MHz XTAL: Xi)
P15[0] (GPIO, MHz XTAL: Xo)
Vccd
Vssd
Vddd
[6]
P15[7]
P15[6]
(USBIO,
(USBIO,
D-, SWDCK)
D+, SWDIO)
[6]
P1[7] (GPIO)
P1[6] (GPIO)
Vddio1
P1[5] (GPIO, nTRST)
P1[4] (GPIO, TDI)
P1[3] (GPIO, TDO, SWV)
P1[2] (GPIO, configurable XRES)
P1[1] (GPIO, TCK, SWDCK)
P1[0] (GPIO, TMS, SWDIO)
Note
6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-56955 Rev. *K
Page 5 of 120
5 Page 
PSoC® 3: CY8C32 Family
Data Sheet
USBIO, D+
Provides D+ connection directly to a USB 2.0 bus. May be used
as a digital I/O pin. Pins are Do Not Use (DNU) on devices
without USB.
USBIO, D–
Provides D– connection directly to a USB 2.0 bus. May be used
as a digital I/O pin. Pins are No Connect (NC) on devices without
USB.
Vboost
Power sense connection to boost pump.
Vbat
Battery supply to boost pump.
Vcca
Output of analog core regulator and input to analog core.
Requires a 1-µF capacitor to VSSA. Regulator output not for
external use.
Vccd
Output of digital core regulator and input to digital core. The two
VCCD pins must be shorted together, with the trace between
them as short as possible, and a 1-µF capacitor to VSSD; see
Power System on page 29. Regulator output not for external use.
Vdda
Supply for all analog peripherals and analog core regulator.
Vdda must be the highest voltage present on the device. All
other supply pins must be less than or equal to VDDA.
Vddd
Supply for all digital peripherals and digital core regulator. VDDA
must be less than or equal to VDDA.
Vssa
Ground for all analog peripherals.
Vssb
Ground connection for boost pump.
Vssd
Ground for all digital logic and I/O pins.
Vddio0, Vddio1, Vddio2, Vddio3
Supply for I/O pins. See pinouts for specific I/O pin to Vddio
mapping. Each Vddio must be tied to a valid operating voltage
(1.71 V to 5.5 V), and must be less than or equal to Vdda. If the
I/O pins associated with Vddio0, Vddio2 or Vddio3 are not used
then that Vddio should be tied to ground (Vssd or Vssa).
XRES (and configurable XRES)
External reset pin. Active low with internal pull-up. Pin P1[2] may
be configured to be a XRES pin; see “Nonvolatile Latches
(NVLs)” on page 23.
4. CPU
4.1 8051 CPU
The CY8C32 devices use a single cycle 8051 CPU, which is fully
compatible with the original MCS-51 instruction set. The
CY8C32 family uses a pipelined RISC architecture, which
executes most instructions in 1 to 2 cycles to provide peak
performance of up to 24 MIPS with an average of 2 cycles per
instruction. The single cycle 8051 CPU runs ten times faster than
a standard 8051 processor.
The 8051 CPU subsystem includes these features:
Single cycle 8051 CPU
Up to 64 KB of flash memory, up to 2 KB of EEPROM, and up
to 8 KB of SRAM
Programmable nested vector interrupt controller
Direct memory access (DMA) controller
Peripheral HUB (PHUB)
External memory interface (EMIF)
4.2 Addressing Modes
The following addressing modes are supported by the 8051:
Direct Addressing: The operand is specified by a direct 8-bit
address field. Only the internal RAM and the SFRs can be
accessed using this mode.
Indirect Addressing: The instruction specifies the register which
contains the address of the operand. The registers R0 or R1
are used to specify the 8-bit address, while the data pointer
(DPTR) register is used to specify the 16-bit address.
Register Addressing: Certain instructions access one of the
registers (R0 to R7) in the specified register bank. These
instructions are more efficient because there is no need for an
address field.
Register Specific Instructions: Some instructions are specific
to certain registers. For example, some instructions always act
on the accumulator. In this case, there is no need to specify the
operand.
Immediate Constants: Some instructions carry the value of the
constants directly instead of an address.
Indexed Addressing: This type of addressing can be used only
for a read of the program memory. This mode uses the data
pointer as the base and the accumulator value as an offset to
read a program memory.
Bit Addressing: In this mode, the operand is one of 256 bits.
Document Number: 001-56955 Rev. *K
Page 11 of 120
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY8C3244.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY8C3244 | Programmable System-on-Chip | Cypress Semiconductor |
| CY8C3245 | Programmable System-on-Chip | Cypress Semiconductor |
| CY8C3246 | Programmable System-on-Chip | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |