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PDF AT91M40807 Data sheet ( Hoja de datos )
| Número de pieza | AT91M40807 | |
| Descripción | AT91 ARM Thumb Microcontroller | |
| Fabricantes | ATMEL Corporation | |
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Features
• Incorporates the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Little-endian
– EmbeddedICE™ (In-circuit Emulation)
• 8-, 16- and 32-bit Read and Write Support
• 256K Bytes of On-chip SRAM
– 32-bit Data Bus
– Single-clock Cycle Access
• Fully Programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to Eight Chip Selects
– Software Programmable 8/16-bit External Data Bus
• Eight-level Priority, Individually Maskable, Vectored Interrupt Controller
– Four External Interrupts, including a High-priority, Low-latency Interrupt Request
• 32 Programmable I/O Lines
• Three-channel 16-bit Timer/Counter
– Three External Clock Inputs
– Two Multi-purpose I/O Pins per Channel
• Two USARTs
– Two Dedicated Peripheral Data Controller (PDC) Channels per USART
• Programmable Watchdog Timer
• Advanced Power-saving Features
– CPU and Peripheral Can be Deactivated Individually
• Fully Static Operation:
– 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85° C
• 2.7V to 3.6V I/O Operating Range
• 1.65V to 1.95V Core Operating Range
• -40° C to +85° C Temperature Range
• Available in 100-lead LQFP Package (Green)
AT91 ARM
Thumb-based
Microcontroller
AT91R40008
Summary
1. Description
The AT91R40008 microcontroller is a member of the Atmel AT91 16/32-bit microcon-
troller family, which is based on the ARM7TDMI processor core. This processor has a
high-performance, 32-bit RISC architecture with a high-density, 16-bit instruction set
and very low power consumption. Furthermore, it features 256K bytes of on-chip
SRAM and a large number of internally banked registers, resulting in very fast excep-
tion handling, and making the device ideal for real-time control applications.
The AT91R40008 microcontroller features a direct connection to off-chip memory,
including Flash, through the fully programmable External Bus Interface (EBI). An 8-
level priority vectored interrupt controller, in conjunction with the Peripheral Data Con-
troller, significantly improves the real-time performance of the device.
The device is manufactured using Atmel’s high-density CMOS technology. By com-
bining the ARM7TDMI processor core with a large, on-chip, high-speed SRAM and a
wide range of peripheral functions on a monolithic chip, the AT91R40008 is a powerful
microcontroller that offers a flexible and high-performance solution to many compute-
intensive embedded control applications.
1732FS–ATARM–12-Apr-06
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
http://www.atmel.com/dyn/resources/prod_documents/doc
1354.pdf
1 page  
AT91R40008
5. Architectural Overview
The AT91R40008 microcontroller integrates an ARM7TDMI with EmbeddedICE interface,
memories and peripherals. The architecture consists of two main buses: the Advanced Sys-
tem Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum performance
and controlled by the memory controller, the ASB interfaces the ARM7TDMI processor with
the on-chip 32-bit memories, the External Bus Interface (EBI) and the AMBA™ Bridge. The
AMBA Bridge drives the APB, which is designed for accesses to on-chip peripherals and opti-
mized for low power consumption.
The AT91R40008 microcontroller implements the ICE port of the ARM7TDMI processor on
dedicated pins, offering a complete, low-cost and easy-to-use debug solution for target
debugging.
5.1 Memories
The AT91R40008 microcontroller embeds 256K bytes of internal SRAM. The internal memory
is directly connected to the 32-bit data bus and is single-cycle accessible.
The AT91R40008 microcontroller features an External Bus Interface (EBI), which enables
connection of external memories and application-specific peripherals. The EBI supports 8- or
16-bit devices and can use two 8-bit devices to emulate a single 16-bit device. The EBI imple-
ments the early read protocol, enabling faster memory accesses than standard memory
interfaces.
5.2 Peripherals
The AT91R40008 microcontrollers integrate several peripherals, that are classified as system
or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and can
be programmed with a minimum number of instructions. The peripheral register set consists of
control, mode, data, status and enable/disable/status registers.
An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs and
on- and off-chip memories address space without processor intervention. Most importantly,
the PDC removes the processor interrupt handling overhead, making it possible to transfer up
to 64K contiguous bytes without reprogramming the start address, thus increasing the perfor-
mance of the microcontroller and reducing the power consumption.
5.2.1
System Peripherals
The External Bus Interface (EBI) controls the external memory or peripheral devices via an 8-
or 16-bit data bus and is programmed through the Advanced Peripheral Bus (APB). Each chip
select line has its own programming register.
The Power-saving (PS) module implements the Idle mode (ARM7TDMI core clock stopped
until the next interrupt) and enables the user to adapt the power consumption of the microcon-
troller to application requirements (independent peripheral clock control).
The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the inter-
nal peripherals and the four external interrupt lines (including the FIQ) to provide an interrupt
and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller and,
using the Auto-vectoring feature, reduces the interrupt latency time.
The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. It enables the user to
select specific pins for on-chip peripheral input/output functions and general-purpose
1732FS–ATARM–12-Apr-06
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AT91R40008
8. Peripherals
The AT91R40008 microcontroller peripherals are connected to the 32-bit wide Advanced
Peripheral Bus. Peripheral registers are only word accessible – byte and half-word accesses
are not supported. If a byte or a half-word access is attempted, the memory controller auto-
matically masks the lowest address bits and generates a word access.
Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte address
space).
8.0.1
Peripheral Registers
The following registers are common to all peripherals:
• Control Register – write-only register that triggers a command when a one is written to the
corresponding position at the appropriate address. Writing a zero has no effect.
• Mode Register – read/write register that defines the configuration of the peripheral. Usually
has a value of 0x0 after a reset.
• Data Registers – read and/or write registers that enable the exchange of data between the
processor and the peripheral.
• Status Register – read-only register that returns the status of the peripheral.
• Enable/Disable/Status Registers are shadow command registers. Writing a one in the
Enable Register sets the corresponding bit in the Status Register. Writing a one in the
Disable Register resets the corresponding bit and the result can be read in the Status
Register. Writing a bit to zero has no effect. This register access method maximizes the
efficiency of bit manipulation and enables modification of a register with a single non-
interruptible instruction, replacing the costly read-modify-write operation.
Unused bits in the peripheral registers are shown as “–” and must be written at 0 for upward
compatibility. These bits read 0.
8.0.2
Peripheral Interrupt Control
The Interrupt Control of each peripheral is controlled from the Status Register using the inter-
rupt mask. The Status Register bits are ANDed to their corresponding interrupt mask bits and
the result is then ORed to generate the Interrupt Source signal to the Advanced Interrupt
Controller.
The interrupt mask is read in the Interrupt Mask Register and is modified with the Interrupt
Enable Register and the Interrupt Disable Register. The enable/disable/status (or mask)
makes it possible to enable or disable peripheral interrupt sources with a non-interruptible sin-
gle instruction. This eliminates the need for interrupt masking at the AIC or Core level in real-
time and multi-tasking systems.
8.0.3
Peripheral Data Controller
The AT91R40008 microcontroller has a 4-channel PDC dedicated to the two on-chip USARTs.
One PDC channel is dedicated to the receiver and one to the transmitter of each USART.
The user interface of a PDC channel is integrated in the memory space of each USART. It
contains a 32-bit Address Pointer Register (RPR or TPR) in addition to a 16-bit Transfer
Counter Register (RCR or TCR). When the programmed number of transfers are performed, a
status bit indicating the end of transfer is set in the USART Status Register and an interrupt
can be generated.
1732FS–ATARM–12-Apr-06
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| PDF Descargar | [ Datasheet AT91M40807.PDF ] | |
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