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PDF DS87C550 Data sheet ( Hoja de datos )
| Número de pieza | DS87C550 | |
| Descripción | EPROM High-Speed Microcontroller | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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www.maxim-ic.com
DS87C550
EPROM High-Speed Microcontroller
with ADC and PWM
FEATURES
§ 87C52 Compatible
- 8051 pin and instruction set compatible
- Three 16-bit timer/counters
- 256 bytes scratchpad RAM
§ On-Chip Memory
- 8kB EPROM (OTP & Windowed Packages)
- 1kB extra on-chip SRAM for MOVX access
§ On-Chip Analog-to-Digital Converter
- Eight channels of analog input, 10-bit
resolution
- Fast conversion time
§ Pulse-Width Modulator Outputs
- Four channels of 8-bit PWM
- Channels cascadable to 16-bit PWM
§ Four Capture plus Three Compare Registers
§ 55 I/O Port Pins
§ New Dual Data Pointer Operation
- Either data pointer can be incremented or
decremented
§ ROMSIZE Feature
- Sets effective on-chip ROM size from 0 - 8kB
- Allows access to entire external memory map
- Dynamically adjustable by software
§ High-Speed Architecture
- 4 clocks/machine cycle (8051 = 12)
- Runs DC to 33MHz clock rates
- Single-cycle instruction in 121ns
- New Stretch Cycle feature allows access to
fast/slow memory or peripherals
§ Unique Power Savings Modes
§ EMI Reduction Mode Disables ALE if Not
Needed
§ High-Integration Controller Includes:
- Power-fail reset
- Early-warning power-fail interrupt
- Two full-duplex hardware serial ports
- Programmable watchdog timer
§ 16 Total Interrupt Sources with Six External
§ Available in 68-Pin PLCC, 80-Pin PQFP, and
68-Pin Windowed CLCC
PIN CONFIGURATIONS
TOP VIEW
9
1
10
61
60
DS87C550
26 44
27 43
PLCC, Windowed CLCC
80 65
1 64
DS87C550
24 41
The High-Speed Microcontroller User’s Guide and High-Speed
Microcontroller User’s Guide: DS87C550 Supplement must be used
in conjunction with this data sheet. Download them at
www.maxim-ic.com/user_guides.
25
PQFP
40
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 070505
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DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
PLCC/
CLCC
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50
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40
41
42
43
44
45
46
24-31
QFP
51-58
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55
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SIGNAL NAME
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
P2.0 (A8)
P2.1 (A9)
P2.2 (A10)
P2.3 (A11)
P2.4 (A12)
P2.5 (A13)
P2.6 (A14)
P2.7 (A15)
P3.0-P3.7
DESCRIPTION
Port 0-I/O - AD0-7. Port 0 is an open-drain 8-bit, bi-directional general-purpose
I/O port. When used in this mode pullup resistors are required to provide a logic 1
output. As an alternate function, Port 0 operates as a multiplexed address/data bus
to access off-chip memory or peripherals. In this mode, the LSB of the memory
address is output on the bus during the time that ALE is high. When ALE falls to
a logic 0, the port transitions to a bi-directional data bus. In this mode, the port
provides active high drivers for logic 1 output. The reset condition of Port 0 is tri-
state (i.e., the open drain devices are off).
Port 2-I/O Address A15:A8. Port 2 functions as an 8-bit bi-directional I/O port
or alternately as an external address bus (A15-A8). The reset condition of Port 2 is
logic high I/O state. In this state, weak pullups hold the port high allowing the
pins to be used as an input or output as described above for Port 1. As an alternate
function Port 2 can function as MSB of the external address bus. This bus can be
used to read external memory or peripherals.
Port 3 - I/O. Port 3 functions as an 8-bit bi-directional I/O port or alternately as
an interface for External Interrupts, Serial Port 0, Timer 0 & 1 Inputs, and RD and
WR strobes. When functioning as an I/O port, these pins operate as indicated
above for Port 1. The alternate modes of Port 3 are detailed below.
24 18
25 19
26 20
27 23
28 24
29 25
30 26
31 27
7-14 80
1-2
4-8
P4.0-P4.7
Port Alternate Mode
P3.0 RXD0 Serial Port 0 Input
P3.1 TXD0 Serial Port 0 Output
P3.2 INT0
External Interrupt 0
P3.3 INT1
P3.4 T0
P3.5 T1
External Interrupt 1
Timer 0 External Input
Timer 1 External Input
P3.6 WR
External Data Memory Write Strobe
P3.7 RD
External Data Memory Read Strobe
Port 4 - I/O. Port 4 functions as an 8-bit bi-directional I/O port or alternately as
an interface to Timer 2’s Capture Compare functions. When functioning as an I/O
port, these pins operate as indicated in the Port 1 description. The alternate modes
of Port 4 are detailed below.
7 80
81
92
10 4
11 5
12 6
13 7
14 8
Port 4 Alternate Mode
P4.0 CMSR0 Timer 2 compare match set/reset output 0
P4.1 CMSR1 Timer 2 compare match set/reset output 1
P4.2 CMSR2 Timer 2 compare match set/reset output 2
P4.3 CMSR3 Timer 2 compare match set/reset output 3
P4.4 CMSR4 Timer 2 compare match set/reset output 4
P4.5 CMSR5 Timer 2 compare match set/reset output 5
P4.6 CMT0 Timer 2 compare match toggle output 0
P4.7 CMT1 Timer 2 compare match toggle output 1
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DS87C550 EPROM High-Speed Microcontroller with ADC and PWM
ROM address of 5k. This would cause the current address to switch from internal to external and
potentially cause invalid operation. Similarly, do not instantly switch from external to internal memory.
For example, do not select a maximum ROM address of 8kB from an external ROM address of 7kB (if
ROMSIZE is set for 4kB or less).
Off-chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2.
While serving as a memory bus, these pins are not available as I/O ports. This convention follows the
standard 8051 method of expanding on-chip memory. Off-chip ROM access also occurs if the EA pin is
logic 0. EA overrides all bit settings. The PSEN signal will go active (low) to serve as a chip enable or
output enable when Ports 0 & 2 fetch from external ROM.
ROM MEMORY MAP Figure 2
DATA MEMORY
Unlike many 8051 derivatives, the DS87C550 contains additional on-chip data memory. In addition to
the standard 256 bytes of data RAM accessed by direct instructions, the DS87C550 contains another 1kB
of data memory that is accessed using the MOVX instruction. Although physically on-chip, software
treats this area as though it was located off-chip. The 1kB of SRAM is permanently located from address
0000h to 03FFh (when enabled).
Access to the on-chip data RAM is optional under software control. When enabled by software, the data
SRAM is between 0000h and 03FFh. Any MOVX instruction that uses this area will go to the on-chip
RAM while enabled. MOVX addresses greater than 1kB automatically go to external memory through
Ports 0 & 2.
When disabled, the 1kB memory area is transparent to the system memory map. Any MOVX directed to
the space between 0000h and FFFFh goes to the expanded bus on Ports 0 & 2. This also is the default
condition. This default allows the DS87C550 to drop into an existing system that uses these addresses for
other hardware and still have full compatibility.
The on-chip data area is software selectable using two bits in the Power Management Register (DME1,
DME0). This selection is dynamically programmable. Thus access to the on-chip area becomes
transparent to reach off-chip devices at the same addresses. These bits have the following operation:
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS87C550.PDF ] | |
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