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PDF DS83C530 Data sheet ( Hoja de datos )
| Número de pieza | DS83C530 | |
| Descripción | EPROM MICRO | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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DS87C530/DS83C530
EPROM/ROM Micro with Real Time Clock
FEATURES
80C52-compatible
- 8051 instruction set-compatible
- Four 8-bit I/O ports
- Three 16-bit timer/counters
- 256 bytes scratchpad RAM
Large on-chip memory
- 16 kB EPROM (OTP)
- 1 kB extra on-chip SRAM for MOVX
ROMSIZE Feature
- Selects effective on-chip ROM size from
0 to 16kB
- Allows access to entire external memory
map
- Dynamically adjustable by software
- Useful as boot block for external Flash
Nonvolatile Functions
- On-chip Real Time Clock w/ Alarm
Interrupt
- Battery backup support of 1 kB SRAM
High-Speed Architecture
- 4 clocks/machine cycle (8051 = 12)
- Runs DC to 33 MHz clock rates
- Single-cycle instruction in 121 ns
- Dual data pointer
- Optional variable length MOVX to access
fast/slow RAM /peripherals
Power Management Mode
- Programmable clock source saves power
- Runs from (crystal/64) or (crystal/1024)
- Provides automatic hardware and software
exit
EMI Reduction Mode disables ALE
Two full-duplex hardware serial ports
High integration controller includes:
- Power-Fail Reset
- Early-Warning Power-Fail Interrupt
- Programmable Watchdog Timer
14 total interrupt sources with 6 external
PACKAGE OUTLINE
71
8
47
46
DALLAS
DS87C530
DS83C530
20 34
21 52-Pin PLCC 33
52-Pin CER QUAD
39 27
40 26
DALLAS
DS87C530
DS83C530
52 14
1 13
52-Pin TQFP OUTLINE
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112299
1 page  
DS87C530/DS83C530
PLCC
30
31
32
33
34
35
36
37
15-22
TQFP
23
24
25
26
27
28
29
30
8-15
SIGNAL
NAME
P2.0 (AD8)
P2.1 (AD9)
P2.2 (AD10)
P2.3 (AD11)
P2.4 (AD12)
P2.5 (AD13)
P2.6 (AD14)
P2.7 (AD15)
P3.0 - P3.7
DESCRIPTION
Port 2 (A8-15) - I/O. Port 2 is a bi-directional I/O port. The reset
condition of Port 2 is logic high. In this state, a weak pullup holds
the port high. This condition also serves as an input mode, since
any external circuit that writes to the port will overcome the weak
pullup. When software writes a 0 to any port pin, the device will
activate a strong pulldown that remains on until either a 1 is
written or a reset occurs. Writing a 1 after the port has been at 0
will cause a strong transition driver to turn on, followed by a
weaker sustaining pullup. Once the momentary strong driver turns
off, the port again becomes both the output high and input state.
As an alternate function Port 2 can function as MSB of the
external address bus. This bus can be used to read external ROM
and read/write external RAM memory or peripherals.
Port 3 - I/O. Port 3 functions as both an 8-bit bi-directional I/O
port and an alternate functional interface for external interrupts,
Serial Port 0, Timer 0 and 1 Inputs, and RD and WR strobes. The
reset condition of Port 3 is with all bits at a logic 1. In this state, a
weak pullup holds the port high. This condition also serves as an
input mode, since any external circuit that writes to the port will
overcome the weak pullup. When software writes a 0 to any port
pin, the device will activate a strong pulldown that remains on
until either a 1 is written or a reset occurs. Writing a 1 after the
port has been at 0 will cause a strong transition driver to turn on,
followed by a weaker sustaining pullup. Once the momentary
strong driver turns off, the port again becomes both the output
high and input state. The alternate modes of Port 3 are outlined
below.
15 8
16 9
17 10
18 11
19 12
20 13
21 14
22 15
42 35
51 44
EA
VBAT
Port Alternate
P3.0 RXD0
P3.1 TXD0
Function
Serial Port 0 Input
Serial Port 0 Output
P3.2 INT0
P3.3 INT1
P3.4 T0
P3.5 T1
External Interrupt 0
External Interrupt 1
Timer 0 External Input
Timer 1 External Input
P3.6 WR
External Data Memory Write Strobe
P3.7 RD
External Data Memory Read Strobe
EA - Input. Connect to ground to use an external ROM. Internal
RAM is still accessible as determined by register settings. Connect
to VCC to use internal ROM.
VBAT - Input. Connect to the power source that maintains SRAM
and RTC when VCC < VBAT. May be connected to a 3V lithium
battery or a super-cap. Connect to GND if battery will not be used
with device.
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DS87C530/DS83C530
pin. The nominal battery voltage is 3V. The VBAT pin will not source current. Therefore, a super cap
requires an external resistor and diode to supply charge.
The backup lifetime is a function of the battery capacity and the data retention current drain. This drain is
specified in the electrical specifications. The circuit loads the VBAT only when VCC has fallen below VBAT.
Thus the actual lifetime depends not only on the current and battery capacity, but also on the portion of
time without power. A very small lithium cell provides a lifetime of more than 10 years.
INTERNAL BACKUP CIRCUIT Figure 3
IMPORTANT APPLICATION NOTE
The pins on the DS87C530/DS83C530 are generally as resilient as other CMOS circuits. They have no
unusual susceptibility to electrostatic discharge (ESD) or other electrical transients. However, no pin on
the DS87C530/DS83C530 should ever be taken to a voltage below ground. Negative voltages on any
pin can turn on internal parasitic diodes that draw current directly from the battery. If a device pin is
connected to the “outside world” where it may be handled or come in contact with electrical noise,
protection should be added to prevent the device pin from going below -0.3V. Some power supplies can
give a small undershoot on power up, which should be prevented. Application Note 93, “Design
Guidelines for Microcontrollers Incorporating NV RAM,” discusses how to protect the
DS87C530/DS83C530 against these conditions.
MEMORY RESOURCES
Like the 8051, the DS87C530/DS83C530 uses three memory areas. The total memory configuration of
the device is 16kB of ROM, 1kB of data SRAM and 256 bytes of scratchpad or direct RAM. The 1kB of
data space SRAM is read/write accessible and is memory mapped. This on-chip SRAM is reached by the
MOVX instruction. It is not used for executable memory. The scratchpad area is 256 bytes of register
mapped RAM and is identical to the RAM found on the 80C52. There is no conflict or overlap among the
256 bytes and the 1 kB as they use different addressing modes and separate instructions.
OPERATIONAL CONSIDERATION
The erasure window of the windowed CERQUAD should be covered without regard to the programmed/
unprogrammed state of the EPROM. Otherwise, the device may not meet the AC and DC parameters
listed in the datasheet.
11 of 44
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS83C530.PDF ] | |
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