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PDF LM4F230H5QR Data sheet ( Hoja de datos )
| Número de pieza | LM4F230H5QR | |
| Descripción | Microcontroller | |
| Fabricantes | Texas | |
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TEXAS INSTRUMENTS-ADVANCE INFORMATION
Stellaris® LM4F230H5QR Microcontroller
DATA SHEET
DS-LM4F230H5QR-14007.2601
SPMS314E
Copyright © 2007-2013
Te xa s In stru me n ts In co rporated
1 page  
Stellaris® LM4F230H5QR Microcontroller
5.4 Register Map .............................................................................................................. 233
5.5 System Control Register Descriptions ........................................................................... 238
5.6 System Control Legacy Register Descriptions ............................................................... 411
6 System Exception Module ................................................................................... 472
6.1 Functional Description ................................................................................................. 472
6.2 Register Map .............................................................................................................. 472
6.3 Register Descriptions .................................................................................................. 472
7 Hibernation Module .............................................................................................. 480
7.1 Block Diagram ............................................................................................................ 481
7.2 Signal Description ....................................................................................................... 481
7.3 Functional Description ................................................................................................. 482
7.3.1 Register Access Timing ............................................................................................... 482
7.3.2 Hibernation Clock Source ............................................................................................ 483
7.3.3 System Implementation ............................................................................................... 484
7.3.4 Battery Management ................................................................................................... 485
7.3.5 Real-Time Clock .......................................................................................................... 486
7.3.6 Battery-Backed Memory .............................................................................................. 488
7.3.7 Power Control Using HIB ............................................................................................. 488
7.3.8 Power Control Using VDD3ON Mode ........................................................................... 488
7.3.9 Initiating Hibernate ...................................................................................................... 488
7.3.10 Waking from Hibernate ................................................................................................ 489
7.3.11 Arbitrary Power Removal ............................................................................................. 489
7.3.12 Interrupts and Status ................................................................................................... 489
7.4 Initialization and Configuration ..................................................................................... 490
7.4.1 Initialization ................................................................................................................. 490
7.4.2 RTC Match Functionality (No Hibernation) .................................................................... 491
7.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 491
7.4.4 External Wake-Up from Hibernation .............................................................................. 491
7.4.5 RTC or External Wake-Up from Hibernation .................................................................. 492
7.5 Register Map .............................................................................................................. 492
7.6 Register Descriptions .................................................................................................. 493
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.3
8.4
8.5
8.6
Internal Memory ................................................................................................... 511
Block Diagram ............................................................................................................ 511
Functional Description ................................................................................................. 512
SRAM ........................................................................................................................ 512
ROM .......................................................................................................................... 513
Flash Memory ............................................................................................................. 515
EEPROM .................................................................................................................... 520
Register Map .............................................................................................................. 526
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 527
EEPROM Register Descriptions (EEPROM Offset) ........................................................ 545
Memory Register Descriptions (System Control Offset) .................................................. 561
9
9.1
9.2
9.2.1
9.2.2
Micro Direct Memory Access (μDMA) ................................................................ 570
Block Diagram ............................................................................................................ 571
Functional Description ................................................................................................. 571
Channel Assignments .................................................................................................. 572
Priority ........................................................................................................................ 573
January 19, 2013
Texas Instruments-Advance Information
5
5 Page 
Stellaris® LM4F230H5QR Microcontroller
List of Figures
Figure 1-1.
Figure 1-2.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 3-1.
Figure 3-2.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 7-1.
Figure 7-2.
Figure 7-3.
Figure 7-4.
Figure 8-1.
Figure 8-2.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 9-5.
Figure 9-6.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 11-4.
Figure 11-5.
Figure 11-6.
Figure 11-7.
Stellaris® Blizzard-class Block Diagram ................................................................ 49
Stellaris LM4F230H5QR Microcontroller High-Level Block Diagram ........................ 51
CPU Block Diagram ............................................................................................. 74
TPIU Block Diagram ............................................................................................ 75
Cortex-M4F Register Set ...................................................................................... 78
Bit-Band Mapping .............................................................................................. 102
Data Storage ..................................................................................................... 103
Vector Table ...................................................................................................... 110
Exception Stack Frame ...................................................................................... 113
SRD Use Example ............................................................................................. 131
FPU Register Bank ............................................................................................ 134
JTAG Module Block Diagram .............................................................................. 204
Test Access Port State Machine ......................................................................... 207
IDCODE Register Format ................................................................................... 213
BYPASS Register Format ................................................................................... 213
Boundary Scan Register Format ......................................................................... 214
Basic RST Configuration .................................................................................... 218
External Circuitry to Extend Power-On Reset ....................................................... 218
Reset Circuit Controlled by Switch ...................................................................... 219
Power Architecture ............................................................................................ 222
Main Clock Tree ................................................................................................ 225
Module Clock Selection ...................................................................................... 232
Hibernation Module Block Diagram ..................................................................... 481
Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 483
Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 484
Using a Regulator for Both VDD and VBAT ............................................................ 485
Internal Memory Block Diagram .......................................................................... 511
EEPROM Block Diagram ................................................................................... 512
μDMA Block Diagram ......................................................................................... 571
Example of Ping-Pong μDMA Transaction ........................................................... 577
Memory Scatter-Gather, Setup and Configuration ................................................ 579
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 580
Peripheral Scatter-Gather, Setup and Configuration ............................................. 582
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 583
Digital I/O Pads ................................................................................................. 637
Analog/Digital I/O Pads ...................................................................................... 638
GPIODATA Write Example ................................................................................. 639
GPIODATA Read Example ................................................................................. 639
GPTM Module Block Diagram ............................................................................ 689
Reading the RTC Value ...................................................................................... 696
Input Edge-Count Mode Example, Counting Down ............................................... 698
16-Bit Input Edge-Time Mode Example ............................................................... 699
16-Bit PWM Mode Example ................................................................................ 701
CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 701
CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 702
January 19, 2013
Texas Instruments-Advance Information
11
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