|
|
PDF STK14C88 Data sheet ( Hoja de datos )
| Número de pieza | STK14C88 | |
| Descripción | 32 K x 8 AutoStore nvSRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de STK14C88 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
|
No Preview Available !
STK14C88
32 K x 8 AutoStore nvSRAM
Features
■ 25 ns, 35 ns, and 45 ns read access and R/W cycle time
■ Unlimited read/write endurance
■ Automatic nonvolatile STORE on power loss
■ Nonvolatile STORE under hardware or software control
■ Automatic RECALL to SRAM on power up
■ Unlimited RECALL cycles
■ 1-Million STORE cycles
■ 100-year nonvolatile data retention
■ Single 5 V + 10% power supply
■ Commercial, industrial, military temperatures
■ 32-Pin 300 mil SOIC (RoHS-compliant)
■ 32-Pin CDIP and LCC packages
Description
The Cypress STK14C88 is a 256 Kb fast static RAM with a
nonvolatile Quantum Trap storage element included with each
memory cell.
The SRAM provides the fast access and cycle times, ease of
use, and unlimited read and write endurance of a normal SRAM.
Data automatically transfers to the nonvolatile storage cells
when power loss is detected (the STORE operation). On power
up, data is automatically restored to the SRAM (the RECALL
operation). Both STORE and RECALL operations are also
available under software control.
The Cypress nvSRAM is the first monolithic nonvolatile memory
to offer unlimited writes and reads. It is the highest performance,
most reliable nonvolatile memory available.
For a complete list of related documentation, click here.
Logic Block Diagram
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Quantum Trap
512 x 512
STATIC RAM
ARRAY
512 x 512
STORE
RECALL
VCCX VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
SOFTWARE
DETECT
A0 - A13
G
E
W
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-52038 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 31, 2015
1 page  
STK14C88
AC Test Conditions
Input pulse levels.................................................... 0 V to 3 V
Input rise and fall times ............................................... <5 ns
Input and output timing reference levels ....................... 1.5 V
Output load........................................................ See Figure 3
Figure 3. AC Output Loading
5.0 V
OUTPUT
255 Ohms
480 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
Capacitance
Parameter[5]
Description
CIN
COUT
Input capacitance
Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
Max
5
7
Unit Conditions
pF V = 0 to 3 V
pF V = 0 to 3 V
Note
5. These parameters are guaranteed but not tested.
Document Number: 001-52038 Rev. *F
Page 5 of 21
5 Page 
STK14C88
nvSRAM Operation
The STK14C88 has two separate modes of operation: SRAM
mode and nonvolatile mode. In SRAM mode, the memory
operates as a standard-fast SRAM. In nonvolatile mode, data is
transferred from SRAM to nonvolatile elements (the STORE
operation) or from nonvolatile elements to SRAM (the RECALL
operation). In this mode, SRAM functions are disabled.
Noise Considerations
The STK14C88 is a high-speed memory and so must have a
high frequency bypass capacitor of approximately 0.1 F
connected between VCAP and VSS, using leads and traces that
are as short as possible. As with all high-speed CMOS ICs,
careful routing of power, ground, and signals helps to prevent
noise problems.
SRAM Read
The STK14C88 performs a read cycle whenever E and G are
low, and W and HSB are high. The address specified on pins
A0-14 determines which of the 32,768 data bytes are accessed.
When the read is initiated by an address transition, the outputs
are valid after a delay of tAVQV (Read cycle #1). If the read is
initiated by E or G, the outputs are valid at tELQV or at tGLQV,
whichever is later (Read cycle #2). The data outputs repeatedly
respond to address changes within the tAVQV access time
without the need for transitions on any control input pins, and
remain valid until another address change or until E or G is
brought high, or W or HSB is brought low.
SRAM Write
A write cycle is performed whenever E and W are low, and HSB
is high. The address inputs must be stable prior to entering the
write cycle and must remain stable until either E or W goes high
at the end of the cycle. The data on the common I/O pins DQ0-7
are written into the memory if it is valid tDVWH before the end of
a W controlled write or tDVEH before the end of an E controlled
write.
Keep G high during the entire write cycle to avoid data bus
contention on common I/O lines. If G is left low, internal circuitry
turns off the output buffers tWLQZ after W goes low.
Power Up RECALL
During power up, or after any low-power condition (VCAP <
VRESET), an internal RECALL request is latched. When VCAP
again exceeds the sense voltage of VSWITCH, a RECALL cycle
is automatically initiated and takes tRESTORE to complete.
If the STK14C88 is in a write state at the end of power-up
RECALL, the SRAM data will be corrupted. To avoid this, a 10 k
resistor should be connected either between W and system VCC
or between E and system VCC.
Document Number: 001-52038 Rev. *F
Software Nonvolatile STORE
The STK14C88 software STORE cycle is initiated by executing
sequential E controlled read cycles from six specific address
locations. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. The program operation copies the SRAM
data into nonvolatile memory. When a STORE cycle is initiated,
further input and output are disabled until the cycle is completed.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence will be
aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed:
1. Read address 0E38 (hex) Valid READ
2. Read address 31C7 (hex) Valid READ
3. Read address 03E0 (hex) Valid READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0FC0 (hex) Initiate STORE cycle
The software sequence must be clocked with E controlled reads.
After the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. Use only read cycles
in the sequence, although it is not necessary that G be low for
the sequence to be valid. After the tSTORE cycle time is fulfilled,
the SRAM is again activated for read and write operation.
Software Nonvolatile RECALL
A software RECALL cycle is initiated with a sequence of read
operations in a manner similar to the software STORE initiation.
To initiate the RECALL cycle, the following sequence of E
controlled read operations must be performed:
1. Read address 0E38 (hex) Valid READ
2. Read address 31C7 (hex) Valid READ
3. Read address 03E0 (hex) Valid READ
4. Read address 3C1F (hex) Valid READ
5. Read address 303F (hex) Valid READ
6. Read address 0C63 (hex) Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and second, the nonvolatile information is transferred
into the SRAM cells. After the tRECALL cycle time, the SRAM is
again ready for read and write operations. The RECALL
operation in no way alters the data in the nonvolatile elements.
The nonvolatile data can be recalled an unlimited number of
times.
AutoStore Mode
The STK14C88 can be powered in one of three modes.
During normal AutoStore operation, the STK14C88 draws
current from VCC to charge a capacitor connected to the VCAP
pin. This stored charge is used by the chip to perform a single
STORE operation. After power up, when the voltage on the VCAP
pin drops below VSWITCH, the part automatically disconnects the
VCAP pin from VCC and initiate a STORE operation.
Page 11 of 21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet STK14C88.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| STK14C88 | 32 K x 8 AutoStore nvSRAM | Cypress Semiconductor |
| STK14C88 | 32Kx8 AutoStore nvSRAM |  Simtek |
| STK14C88-3 | 32Kx8 AutoStore nvSRAM | Simtek |
| STK14C88-M | 32K x 8 AUTOSTORE nvSRAM QUANTUM TRAP CMOS NONVOLATILE STATIC RAM | Simtek |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |