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PDF CY7C10612DV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C10612DV33 | |
| Descripción | 16-Mbit (1M x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C10612DV33
16-Mbit (1M × 16) Static RAM
16-Mbit (1M × 16) Static RAM
Features
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 175 mA at 100 MHz
■ Low CMOS standby power
❐ ISB2 = 25 mA
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
■ Automatic Power-down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 54-pin TSOP II package
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
INPUT BUFFER
1M x 16
ARRAY
COLUMN
DECODER
Functional Description
The CY7C10612DV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, take Chip Enables (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A19). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A19).
To read from the device, take Chip Enables (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See Truth Table on page 10 for a
complete description of Read and Write modes.
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
The CY7C10612DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout.
For a complete list of related documentation, click here.
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-49315 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 29, 2016
1 page  
CY7C10612DV33
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [4]
OUTPUT
Z0 = 50
50
30 pF*
VTH = 1.5 V
HIGH Z CHARACTERISTICS: R1 317
3.3 V
OUTPUT
5 pF*
(a)
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
3.0 V
90%
GND
10%
RISE TIME:
> 1 V/ns
ALL INPUT PULSES
(c)
INCLUDING
JIG AND
SCOPE (b)
90%
10%
FALL TIME:
> 1 V/ns
R2
351
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min Typ [5] Max Unit
VDR VCC for data retention
2 – –V
ICCDR
Data retention current
VCC = 2 V, CE VCC – 0.2 V,
VIN VCC – 0.2 V or VIN 0.2 V
–
– 25 mA
tCDR [6]
Chip deselect to data retention time
0 – – ns
tR [7] Operation recovery time
tRC –
– ns
Data Retention Waveform
Figure 3. Data Retention Waveform
VCC
CE
3.0 V
tCDR
DATA RETENTION MODE
VDR > 2 V
3.0 V
tR
Notes
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating
VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full device operation requires linear VCC ramp from VDR to VCC(min.) 50 s or stable at VCC(min.) 50 s.
Document Number: 001-49315 Rev. *E
Page 5 of 14
5 Page 
CY7C10612DV33
Package Diagrams
Figure 9. 54-pin TSOP Type II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160
51-85160 *E
Document Number: 001-49315 Rev. *E
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY7C10612DV33.PDF ] | |
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