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PDF CY7C1046DV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1046DV33 | |
| Descripción | 4-Mbit (1 M x 4) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1046DV33
4-Mbit (1 M × 4) Static RAM
4-Mbit (1 M × 4) Static RAM
Features
■ Pin- and function-compatible with CY7C1046CV33
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 90 mA @ 100 MHz
■ Low CMOS standby power
❐ ISB2 = 10 mA
■ 2.0 V data retention
■ Automatic power-down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in lead-free 400-mil-wide 32-pin SOJ package
Logic Block Diagram
Functional Description
The CY7C1046DV33 is a high-performance CMOS static RAM
organized as 1M words by 4 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tri-state drivers. Writing to the device is
accomplished by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3)
is then written into the location specified on the address pins (A0
through A19).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The four input/output pins (I/O0 through I/O3) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a Write operation
(CE LOW, and WE LOW).
The CY7C1046DV33 is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground
(revolutionary) pinout.
For a complete list of related documentation, click here.
A0
A1
A2
AA34
AA56
AA78
A9
A10
CE
WE
OE
INPUT BUFFER
1 Mbit x 4
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05611 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 19, 2014
1 page  
CY7C1046DV33
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [3]
OUTPUT
Z = 50
* capacitive load consists
of all components of the
test environment
High Z characteristics:
3.3 V
R 317
50
1.5 V
(a)
OUTPUT
5 pF
R2
351
(c)
30 pF*
3.0 V
GND
ALL INPUT PULSES
90%
90%
10%
10%
Rise Time: 1 V/ns
(b) Fall Time: 1 V/ns
Note
3. AC characteristics (except high Z) are tested using the load conditions shown in Figure 2 (a). High Z characteristics are tested for all speeds using the test load
shown in Figure 2 (c).
Document Number: 38-05611 Rev. *F
Page 5 of 14
5 Page 
CY7C1046DV33
Package Diagram
Figure 9. 32-pin SOJ (400 Mils) V32.4 (Molded SOJ V33) Package Outline, 51-85033
51-85033 *E
Document Number: 38-05611 Rev. *F
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY7C1046DV33.PDF ] | |
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