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PDF CY7C1019D Data sheet ( Hoja de datos )
| Número de pieza | CY7C1019D | |
| Descripción | 1-Mbit (128 K x 8) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1019D
1-Mbit (128 K × 8) Static RAM
1-Mbit (128 K × 8) Static RAM
Features
■ Pin- and function-compatible with CY7C1019B
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 80 mA @ 10 ns
■ Low CMOS standby power
❐ ISB2 = 3 mA
■ 2.0 V Data retention
■ Automatic power-down when deselected
■ CMOS for optimum speed/power
■ Center power/ground pinout
■ Easy memory expansion with CE and OE options
■ Functionally equivalent to CY7C1019B
■ Available in Pb-free 32-pin 400-Mil wide Molded SOJ and
32-pin TSOP II packages
Logic Block Diagram
Functional Description
The CY7C1019D [1] is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tri-state drivers. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected. The eight input and output pins
(IO0 through IO7) are placed in a high-impedance state when:
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH)
■ When the write operation is active (CE LOW, and WE LOW).
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is
then written into the location specified on the address pins (A0
through A16).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appears on the IO pins.
The CY7C1019D device is suitable for interfacing with
processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
For a complete list of related documentation, click here.
A0
A1
A2
A3
A4
A5
A6
A7
A8
CE
WE
OE
INPUT BUFFER
128K x 8
ARRAY
COLUMN DECODER
POWER
DOWN
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05464 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 26, 2014
1 page  
CY7C1019D
Capacitance
Parameter [4]
Description
CIN
COUT
Input capacitance
Output capacitance
Thermal Resistance
Parameter [4]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 5.0 V
Max Unit
6 pF
8 pF
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
400-Mil Wide
SOJ
56.29
38.14
TSOP II
62.22
21.43
Unit
C/W
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [5]
OUTPUT
Z = 50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
50
1.5V
(a)
30 pF*
3.0 V
GND
ALL INPUT PULSES
90%
90%
10%
10%
Rise Time: 3 ns
(b) Fall Time: 3 ns
High Z characteristics:
R1 480
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5 pF
(c)
R2
255
Notes
4. Tested initially and after any design or process changes that may affect these parameters.
5. AC characteristics (except High Z) are tested using the load conditions shown in Figure 2 (a). High Z characteristics are tested for all speeds using the test load shown
in Figure 2 (c).
Document Number: 38-05464 Rev. *J
Page 5 of 16
5 Page 
CY7C1019D
Truth Table
CE OE
HX
LL
LX
LH
WE IO0–IO7
X High Z
H Data Out
L Data In
H High Z
Mode
Power-Down
Read
Write
Selected, Outputs Disabled
Power
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Ordering Information
Speed
(ns)
Ordering Code
10 CY7C1019D-10VXI
CY7C1019D-10ZSXI
Package
Diagram
Package Type
51-85033 32-pin SOJ (400 Mils) Pb-free
51-85095 32-pin TSOP (Type II) Pb-free
Operating
Range
Industrial
Please contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 7 C 1 01 9 D - 10 XX X I
Temperature Range:
I = Industrial
Pb-free
Package Type: XX = V or ZS
V = 32-pin Molded SOJ
ZS = 32-pin TSOP Type II
Speed: 10 ns
Process Technology: D = C9, 90 nm Technology
Data Width: 9 = × 8-bits
Density: 01 = 1-Mbit density
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05464 Rev. *J
Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CY7C1019D.PDF ] | |
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