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PDF CY7C1018DV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1018DV33 | |
| Descripción | 1-Mbit (128 K x 8) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1018DV33
1-Mbit (128 K × 8) Static RAM
1-Mbit (128 K × 8) Static RAM
Features
■ Pin- and function-compatible with CY7C1018CV33
■ High speed
❐ tAA = 10 ns
■ Low Active Power
❐ ICC = 60 mA @ 10 ns
■ Low CMOS Standby Power
❐ ISB2 = 3 mA
■ 2.0V Data retention
■ Automatic power-down when deselected
■ CMOS for optimum speed/power
■ Center power/ground pinout
■ Easy memory expansion with CE and OE options
■ Available in Pb-free 32-pin 300-Mil wide Molded SOJ
Functional Description
The CY7C1018DV33 is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tri-state drivers. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the eight I/O pins
(I/O0 through I/O7) is then written into the location specified on
the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW).
The CY7C1018DV33 is available in Pb-free 32-pin 300-Mil wide
Molded SOJ.
Logic Block Diagram
A0
A1
A2
AAA345
AA67
A8
CE
WE
OE
INPUTBUFFER
128 K × 8
ARRAY
COLUMN
DECODER
POWER
DOWN
SOJ
Top View
A0 1
32
A1 2
31
A2 3
30
I/O0
A3 4
CE 5
29
28
I/O1
I/O0 6
I/O1 7
27
26
I/O2
VCC
V SS
8
9
25
24
I/O3
I/O2 10
23
I/O3 11
22
I/O4
WE 12
21
I/O5
A4 13
A5 14
20
19
I/O6
A6 15
A7 16
18
17
I/O7
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05465 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 24, 2014
1 page  
CY7C1018DV33
Capacitance
Parameter [2]
Description
CIN
COUT
Input Capacitance
Output Capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = 3.3 V
Max Unit
8 pF
8 pF
Thermal Resistance
Parameter [2]
Description
JA Thermal Resistance
(Junction to Ambient)
JC Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, four-layer printed
circuit board
32-pin SOJ
57.61
40.53
Unit
C/W
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [3]
OUTPUT
Z = 50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
50
1.5 V
(a)
30 pF*
3.0 V
GND
ALL INPUT PULSES
90%
90%
10%
10%
Rise Time: 1 V/ns
(b) Fall Time: 1 V/ns
High-Z characteristics: R 317
3.3 V
OUTPUT
5 pF
R2
351
(c)
Notes
2. Tested initially and after any design or process changes that may affect these parameters.
3. AC characteristics (except High-Z) are tested using the load conditions shown in Figure 2 (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure 2 (c).
Document Number: 38-05465 Rev. *G
Page 5 of 15
5 Page 
CY7C1018DV33
Ordering Information
Speed
(ns)
Ordering Code
10 CY7C1018DV33-10VXI
Package
Diagram
Package Type
51-85041 32-pin (300-Mil) Molded SOJ (Pb-free)
Ordering Code Definitions
CY 7 C 1 01 8 D V33 - 10 V X I
Temperature Range:
I = Industrial
Pb-free
Package Type:
V = 32-pin Molded SOJ
Speed: 10 ns
Voltage range: V33 = 3 V to 3.6 V
Process Technology: D = C9, 90 nm
Bus width: × 8
01 = 1-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Please contact your local Cypress sales representative for availability of these parts.
Operating
Range
Industrial
Document Number: 38-05465 Rev. *G
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CY7C1018DV33.PDF ] | |
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